Low-Noise Amplifier Without ESD Protection

2.2.1. Differential LNA Design

Differential configuration is popular for LNA design because differential LNA has the advantages of common-mode noise rejection, less sensitivity to substrate noise, supply noise, and bond-wire inductance variation. In addition, the differential output signals of the differential LNA can be directly connected to the differential inputs of the double balanced mixer.

There are several requirements on the performance of LNA. First, the noise figure of LNA should be minimized because it dominates overall noise figure of the whole RF receiver.

Besides, the power gain of LNA should be high enough to suppress the impacts caused by the noise figures in the succeeding stages in RF receiver. Moreover, the power consumption needs to be low enough to facilitate portable applications.

The circuit schematic of the LNA without ESD protection for comparison reference is shown in Fig. 2.1. The architecture of common-source with inductive degeneration is applied to match the input impedance of LNA to the source impedance (50 Ω) at the operating frequency of 5 GHz. Good isolation between the input and output can be enhanced by using the cascode configuration. Moreover, the cascode configuration reduces Miller effect and provides good stability [58]. The dimensions of the input NMOS transistors M1 and M3 were designed according to the compromise between noise figure and power consumption. Since the small-signal operation of the differential LNA is symmetrical, the half circuit can be referred to analyze the LNA. The input impedance (Zin) of the RF IN1 pad can be calculated as where Cgs1 is the gate-source capacitance of M1, CG1 is the added capacitance between the gate and source terminals of M1, LG1 is the gate inductance, and LS1 is the source inductance.

The ωT is the unity-gain angular frequency of M1, which can be expressed as

1 where gm1 is the transconductance of M1. With the input matching network resonating at the operating frequency, the input impedance (Zin_Resonance) is purely real and can be given by

1 To match the input impedance at resonance to the source impedance, LS1 is determined once the size of M1 has been chosen. The resonance angular frequency (ω0), which is designed to be the operating frequency, can be obtained by

0 1 1

Fig. 2.1. Differential LNA without ESD protection for comparison reference.

At resonance, the source inductor LS1 and gate inductor LG1 compensate the capacitance at the gate terminal of M1. After LS1 is determined to match the source impedance, the remaining capacitive impedance needs to be cancelled by LG1. However, the small Cgs1 leads to intolerable large LG1. Therefore, an extra capacitor CG1 is added in parallel with Cgs1 to reduce the required inductance of LG1. The drain inductor LD1 and drain capacitor CD1 form the output matching network to match the output impedance of LNA to 50 Ω.

The gate voltages of M2 and M4 are biased to VDD through the resistor R1. The capacitor C1 acts as a decoupling capacitor. LTANK and CTANK form a LC-tank to enhance the common-mode rejection. With the deep N-well structure, the P-well (bulk) region of each NMOS transistor can be fully isolated from the common P-substrate, so the source and bulk terminals are connected together to eliminate the body effect. All of the inductors are the on-chip spiral inductors implemented by the top metal layer, and all of the capacitors in the differential LNA are realized by the metal-insulator-metal (MIM) capacitors. The aforementioned active and passive devices are fully integrated in the experimental test chip in a 130-nm CMOS process. In order to verify the effectiveness of the on-chip ESD protection circuits at the input pads, the ac coupling capacitor between the input pad and LG1 (LG2) is not realized in the test chip, because the ac coupling capacitor connected to the input pad can block some ESD energy when the input pad is stressed by ESD. Thus, the off-chip bias tee is

needed to combine the RF input signal and the dc bias at the input node during RF measurement.

2.2.2. Experimental Results

On-wafer measurements were performed to characterize the RF performance and ESD robustness. The differential LNA without ESD protection consumes 10.3 mW under 1.2-V power supply. To measure the S-parameters of the differential LNA, four-port S-parameter measurement with Agilent E8361A network analyzer was performed. The measurement system converted the measured four-port S-parameters to the differential two-port S-parameters. Fig. 2.2 shows the measured S-parameters of the differential LNA without ESD protection. At 5 GHz, the S11-, S21-, and S22-parameters are -27.2 dB, 16.2 dB, and -9.3 dB, respectively. The measured output matching condition (S22-parameter) is not as good as expectation due to the drain capacitances (CD1 and CD2), which are sensitive to the parasitic effects at the output node. The S12-parameter is better than -29 dB because good reverse isolation is one of the advantages of the cascode configuration. The noise figure was measured by using Agilent N8975A noise figure analyzer and Agilent 346C noise source. The reference differential LNA has the noise figure of 2.16 dB at 5 GHz.

Fig. 2.2. Measured S-parameters of the differential LNA without ESD protection.

The human-body-model (HBM) and machine-model (MM) ESD levels were also measured from the differential LNAs. The failure criterion is 30% voltage shift under 1-μA current bias. During ESD tests, the off-chip bias tee was not included. The measured HBM

and MM ESD levels of the LNAs are listed in Table 2.1. The LNA without ESD protection is very vulnerable to ESD, because it fails at 50-V HBM and 10-V MM ESD tests.

Table 2.1

HBM and MM ESD Robustness Under Different Test Pin Combinations LNA Without

2.3. Differential LNA With Conventional Double-Diode ESD