Measured RF Performance After ESD Zapping

The S-parameters of the UWB RF PA were measured by using the Agilent E8364B PNA.

An Agilent E4448A spectrum analyzer and an Agilent E8257D signal generator were used to evaluate the large signal characteristics of the PA. To compare the ESD protection capability between the PA with and without ESD protection circuit, the RF performance of PA was measured again after each HBM ESD zapping.

(a)

(b)

Fig. 4.16. Die photos of the fabricated (a) unprotected PA and (b) ESD-protected PA.

The measured results of the S22 from 2 to 12 GHz of the PA without ESD protection circuit (unprotected PA) and that of the PA with ESD protection circuit (ESD-protected PA) are shown in Figs. 4.17 and 4.18. The measured results of the S21 are shown in Figs. 4.19 and

4.20. The unprotected PA was severely degraded after HBM or MM ESD zapping. On the contrast, the ESD-protected PA still well performed even if the 8-kV HBM or 800-V MM ESD test was stressed. The bandwidths of the unprotected and ESD-protected PA after each HBM ESD zapping are summarized in Table 4.2. The bandwidths of ESD-protected PA are kept at ~9 dB, even if there are some variations among the test chips.

(a) (b)

Fig. 4.17. Measured results on S₂₂-parameter of (a) unprotected PA, and (b) ESD-protected PA, after each HBM ESD zapping.

(a) (b)

Fig. 4.18. Measured results on S₂₂-parameter of (a) unprotected PA, and (b) ESD-protected PA, after each MM ESD zapping.

(a) (b)

Fig. 4.19. Measured results on S₂₁-parameter of (a) unprotected PA, and (b) ESD-protected PA, after each HBM ESD zapping.

(a) (b)

Fig. 4.20. Measured results on S21-parameter of (a) unprotected PA, and (b) ESD-protected PA, after each MM ESD zapping.

Table 4.2

Bandwidth and Gain of UWB RF PA After HBM ESD Zapping

Bandwidth Averaged Gain (3.1-10.6 GHz) HBM ESD Zapping Unprotected

PA

ESD-Protected PA

Unprotected PA

ESD-Protected PA 0 V 7.8 GHz 7.3 GHz 12.4 dB 9.8 dB 1 kV 7.7 GHz 7.4 GHz 8.9 dB 9.3 dB 2 kV 8.2 GHz 7.3 GHz -0.4 dB 9.2 dB 4 kV 0 GHz 7.4 GHz -51.8 dB 8.5 dB 8 kV 0 GHz 7.3 GHz -55.3 dB 9.5 dB

The averaged large signal power gain of the unprotected and ESD-protected PA within 3.1-10.6 GHz after each HBM ESD zapping are also listed in Table 4.2. According to the measured data, both the bandwidth and the averaged large signal gain of the ESD-protected PA are kept fine after each HBM ESD stress, while those of the unprotected PA are seriously degraded. When the output power increases, the output swing would be compressed. The output power at 1-dB compression point (OP1dB) can be treated as the maximum linear output power capability of the PA. Figs. 4.21 and 4.22 show the measured results on the OP1dB of the unprotected and ESD-protected PA. The OP1dB of the unprotected PA was seriously degraded after HBM or MM ESD zapping. The OP1dB of the ESD-protected PA was not degraded even after 8-kV HBM or 800-V MM ESD test.

(a) (b)

Fig. 4.21. Measured results of OP1dB of (a) unprotected PA, and (b) ESD-protected PA, after each HBM ESD zapping.

(a) (b)

Fig. 4.22. Measured results of OP1dB of (a) unprotected PA, and (b) ESD-protected PA, after each MM ESD zapping.

4.5. Summary

The low-capacitance ESD device is a waffle-structured SCR with trigger circuit incorporated in the whole-chip ESD protection architecture which utilizes an upward diode string to divert part of the ESD current to the power-rail and activate the detection circuit, trigger circuit, and the power-rail ESD clamp. The SCR and the diodes are in waffle-structured layout style which can maximize the discharging peripheral within a given layout area. Therefore, the waffle-structured layout style can provide maximum ESD protection capability but contributing minimum parasitic capacitance. This ESD protection strategy is designed and fabricated in a standard 130-nm CMOS process. A 3-to-10-GHz 0-dBm ultra-wideband class-AB distributed amplifier is designed and acts as the protected RF PA. The waffle-structured SCR and diodes are plugged to RF PA to provide ESD protection. Unprotected PA and ESD-protected PA are tested to understand the influence of ESD zapping. The measurement results prove that an unprotected PA cannot survive any ESD zapping. The gain and output power capability of an unprotected PA are largely degraded ever since a 1-kV HBM test. It can be concluded that an unprotected RF PA may not survive any single ESD zapping; RF PA circuitry is in urgent need of ESD protection.

Besides, the measurement results verify the low-capacitance ESD protection strategy and reveal the truth that this ESD protection technique indeed provides excellent ESD robustness. The RF performance degradation can be minimized by using ESD protection design with the waffle-structured SCR.

Chapter 5

Modeling Parasitic Capacitance for Matching Network Co-Designed in RF ICs

ESD protection design for RF circuits is one of the key challenges to implement RF circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause performance degradations to RF circuits. The performance degradations are much serious for the RF circuits applied to higher frequency band. Therefore, ESD protection circuits must be designed with minimum negative impact to the RF circuits and to sustain high enough ESD robustness. In this chapter, ESD protection design considerations and matching network co-designed in RF ICs are presented and discussed. In section 5.2, the small-signal model of SCR in RF frequency band is presented firstly. With the matching network co-design between SCR device and RF circuits, the parasitics of the SCR device can be cancelled. In section 5.3, the low-capacitance and low-loss bond pad is studied in CMOS technologies for RF ESD applications. Besides, some ESD protection design techniques for RF applications in standard CMOS processes are overviewed in section 5.4.

5.1. Background

ESD protection design on RF circuits applied to higher frequency band is a popular topic.

For example, WirelessHD is the recent technology that operates near the 60-GHz range. To apply the ESD protection devices to such RF circuits, the RF performance degradations caused by the ESD protection devices should be characterized carefully. The implementations of low-capacitance ESD protection device and low-capacitance bond pad are required for RF ICs. Besides, during the RF circuit design, the simulation on RF performances must be performed to acquire preliminary insight into the impacts of ESD protections on RF performance. If all device models of ESD protection device and bond pad in the desired RF frequency band can be obtained, the input/output matching for RF circuits can be well designed. Thus, the circuit simulation models of ESD protection devices have strongly requested by IC industry [75], [76].

SCR has been reported as the useful ESD protection device in RF ICs due to its high ESD robustness within a small layout area and low parasitic capacitance. The macro model of SCR has been reported to simulate its turn-on mechanism during ESD stress [63], [64].

However, the small-signal model of SCR in RF circuit operation condition is scarce. In the RF circuits with SCR-based ESD protection, the lack of SCR device model will introduce the unexpected results, such as the operating frequency shift. To correctly predict the performances of RF circuit with SCR-based ESD protection, it is essential for RF circuit design with accurate model of SCR device. With such a small-signal model, the parasitic capacitance from ESD protection device can be well co-designed with RF circuits.