Conclusions and Future Works
7.2. Future Works
The designs for RF circuits applied to higher frequency band is a popular topic in advanced CMOS technology. The V band occupied from 40 to 75 GHz frequency band. The V band is primarily used for high capacity and short distance communication systems. For example, WirelessHD is the recent technology that operates near the 60-GHz range. To achieve successful ESD protection design for such high-frequency RF circuits, precise modeling of ESD protection devices is necessary. Hence, modeling of ESD protections in such high frequency bands is needed.
In an fully integrate SoC chip with RF frond-end and baseband circuits, the larger die size for SoC applications and the thinner gate oxide in nanoscale CMOS transistors will become the design concerns. With the larger die size and the thinner gate oxide, nanoscale CMOS ICs are very sensitive to charged-device model (CDM) ESD events. Therefore, the efficient CDM ESD protections should be designed in nanoscale CMOS process.
Inductors are often used to compensate the parasitic capacitance of ESD protection devices in RF bands. Besides, the inductor can act like the conductive path under ESD stress conditions, which can be used as the ESD detection circuit for the trigger design on SCR devices. Thus, developing inductor-based ESD detection circuit for SCR devices in RF
circuits is promising in the future.
References
[1] S. Voldman, ESD: Circuits and Devices, John Wiley & Sons, 2006.
[2] S. Voldman, ESD: RF Technology and Circuits. John Wiley & Sons, 2006.
[3] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley &
Sons, 2002.
[4] S. Dabral and T. Maloney, Basic ESD and I/O Design. John Wiley & Sons, 1998.
[5] Electrostatic Discharge (ESD) Sensitivity Testing―Human Body Model (HBM), EIA/JEDEC Standard Test Method 5.1, 2001.
[6] Electrostatic Discharge (ESD) Sensitivity Testing―Machine Model (MM), EIA/JEDEC Standard Test Method 5.2, 1999.
[7] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao, “ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,” in Proc. IEEE Radio Freq.
Integrated Circuit Symp., 2002, pp. 427-430.
[8] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp.
173-183, Jan. 1999.
[9] C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, “Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18um CMOS process,” in Proc. EOS/ESD Symp., 2000, pp. 251-259.
[10] M.-D. Ker and C.-M. Lee, “Interference of ESD protection diodes on RF performance in giga-Hz RF circuits,” in Proc. IEEE Int. Symp. Circuits and Systems, 2003, pp.
297-300.
[11] K. Gong, H. Feng, R. Zhan, and A. Wang, “A study of parasitic effects of ESD protection on RF ICs,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 393-402, Jan. 2002.
[12] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, 1998.
[13] G. Boselli, J. Rodriguez, C. Duvvury, and J. Smith, “Analysis of ESD protection components in 65-nm CMOS technology: scaling perspective and impact on ESD design windows,” in Proc. EOS/ESD Symp., 2005, pp. 43-52.
[14] P. Leroux, M. Steyaert, V. Vassilev, and G. Groeseneken, “A 1.3dB NF CMOS LNA for GPS with 3kV HBM ESD-protection,” in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 335-338.
[15] M.-D. Ker, T.-Y. Chen, and C.-Y. Chang, “ESD protection design for CMOS RF integrated circuits,” in Proc. EOS/ESD Symp., 2001, pp. 346-354.
[16] M.-D. Ker and C.-Y. Chang, “ESD protection design for CMOS RF integrated circuits using polysilicon diodes,” J. Microelectron. Reliab., vol. 42, no. 6, pp. 863-872, Jun.
2002.
[17] X. Jin, L. Tse, K. Tsai, G. Chien, and S. Wei, “Methods and apparatus for improving high frequency input/output performance,” U.S. Patent 6911739, Jun. 2005.
[18] X. Jin, L. Tse, K. Tsai, G. Chien, and S. Wei, “Methods and apparatus for improving high frequency input/output performance,” U.S. Patent 6977444, Dec. 2005.
[19] X. Jin, L. Tse, K. Tsai, G. Chien, and S. Wei, “Methods and apparatus for improving high frequency input/output performance,” U.S. Patent 6987326, Jan. 2006.
[20] X. Jin, L. Tse, K. Tsai, G. Chien, and S. Wei, “Methods and apparatus for improving high frequency input/output performance,” U.S. Patent 7009308, Mar. 2006.
[21] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Comprehensive ESD protection for RF inputs,” J. Microelectron. Reliab., vol. 45, no. 2, pp. 245-254, Feb. 2005.
[22] S. Hyvonen and E. Rosenbaum, “Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs,” in Proc. EOS/ESD Symp., 2005, pp. 9-17.
[23] T. Tsukada, Y. Hashimoto, K. Sakata, H. Okada, and K. Ishibashi, “An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs,”
IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 67-79, Jan. 2005.
[24] M.-D. Ker, C.-M. Lee, and W.-Y. Lo, “Electrostatic discharge protection device for giga-Hz radio frequency integrated circuits with varactor-LC tanks,” U.S. Patent 6885534, Apr. 2005.
[25] M.-D. Ker, C.-M. Lee, and T.-Y. Chen, “Electrostatic discharge protection designs with parallel LC tank for giga-Hz RF integrated circuits,” U.S. Patent 7009826, Mar. 2006.
[26] M.-D. Ker, C.-M. Lee, and T.-Y. Chen, “ESD protection designs with parallel LC tank for giga-Hz RF integrated circuits,” U.S. Patent 7023677, Apr. 2006.
[27] M.-D. Ker, C.-M. Lee, and T.-Y. Chen, “ESD protection designs with parallel LC tank for giga-Hz RF integrated circuits,” U.S. Patent 7023678, Apr. 2006.
[28] M.-D. Ker, C.-I. Chou, and C.-M. Lee, “A novel LC-tank ESD protection design for giga-Hz RF circuits,” in Proc. IEEE Radio Freq. Integrated Circuit Symp., 2003, pp.
115-118.
[29] C. Yue, S. Wong, D. Su, and W. McFarland, “System for providing electrostatic discharge protection for high-speed integrated circuits,” U.S. Patent 6509779, Jan.
2003.
[30] C. Yue, S. Wong, D. Su, and W. McFarland, “System for providing electrostatic discharge protection for high-speed integrated circuits,” U.S. Patent 6593794, Jul. 2003.
[31] C. Yue, S. Wong, D. Su, and W. McFarland, “System for providing electrostatic discharge protection for high-speed integrated circuits,” U.S. Patent 6597227, Jul. 2003.
[32] J. Leete, “Electrostatic protection circuit with impedance matching for radio frequency integrated circuits,” U.S. Patent 6771475, Aug. 2004.
[33] B.-S. Huang and M.-D. Ker, “New matching methodology of low-noise amplifier with ESD protection,” in Proc. IEEE Int. Symp. Circuits and Systems, 2006, pp. 4891-4894.
[34] J. Zerbe, V. Stojanovic, M. Horowitz, and P. Chau, “Input/output circuit with on-chip inductor to reduce parasitic capacitance,” U.S. Patent 7005939, Feb. 2006.
[35] A. Rofougaran, “Radio frequency integrated circuit electro-static discharge circuit,” U.S.
Patent 7010279, Mar. 2006.
[36] D. Linten, S. Thijs, M. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S.
Jenei, S. Donnay, and S. Decoutere, “A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1434-1442, Jul. 2005.
[37] P. Leroux and M. Steyaert, “A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM,” in Proc. Eur. Solid-State Circuits Conf., 2004, pp.
295-298.
[38] J. Borremans, S. Thijs, P. Wambacq, D. Linten, Y. Rolain, and M. Kuijk, “A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA,” in Symp. VLSI Circuits Dig. Tech.
Papers, 2007, pp. 100-101.
[39] S. Galal and B. Razavi, “Broadband ESD protection circuits in CMOS technology,”
IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2334-2340, Dec. 2003.
[40] M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T.
Toifl, and M. Schmatz, “A T-coil-enhanced 8.5Gb/s high-swing source-series-terminated transmitter in 65nm bulk CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 110-111.
[41] D. Linten, S. Thijs, J. Borremans, M. Dehan, D. Tremouilles, M. Scholz, M. Natarajan, P. Wambacq, and G. Groeseneken, “T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology,” in Proc. EOS/ESD Symp., 2007, pp. 242-249.
[42] B. Kleveland and T. Lee, “Distributed ESD protection device for high speed integrated
[43] B. Kleveland, T. Maloney, I. Morgan, L. Madden, T. Lee, and S. Wong, “Distributed ESD protection for high-speed integrated circuits,” IEEE Electron Device Lett., vol. 21, no. 8, pp. 390-392, Aug. 2000.
[44] C. Ito, K. Banerjee, and R. Dutton, “Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs,” IEEE Trans. Electron Devices, vol.
49, no. 8, pp. 1444-1454, Aug. 2002.
[45] M.-D. Ker and B.-J. Kuo, “Decreasing-size distributed ESD protection scheme for broadband RF circuits,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 582-589, Feb. 2005.
[46] M.-D. Ker, B.-J. Kuo, and Y.-W. Hsiao, “Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme,” J. Electrostatics, vol. 64, no. 2, pp. 80-87, Feb. 2006.
[47] M.-D. Ker and C.-M. Lee, “ESD protection circuits with impedance matching for radio-frequency applications,” U.S. Patent 2006/0256489 A1, Nov. 2006.
[48] D. Cassan and J. Long, “A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp.
427-435, Mar. 2003.
[49] C.-H. Liao and H.-R. Chuang, “A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiver,” IEEE Microw. Wireless Compon. Lett., vol. 13, no. 12, pp. 526-528, Dec. 2003.
[50] W. Zhuo, X. Li, S. Shekhar, S. Embabi, J. Pineda de Gyvez, D. Allstot, and E.
Sanchez-Sinencio, “A capacitor cross-coupled common-gate low-noise amplifier,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 12, pp. 875-879, Dec. 2005.
[51] R. Salerno, M. Tiebout, H. Paule, M. Streibl, C. Sandner, and K. Kropf, “ESD-protected CMOS 3-5GHz wideband LNA+PGA design for UWB,” in Proc. Eur. Solid-State Circuits Conf., 2005, pp. 219-222.
[52] A. Bevilacqua, C. Sandner, A. Gerosa, and A. Neviani, “A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 3, pp. 134-136, Mar. 2003.
[53] T. Chang, J. Chen, L. Rigge, and J. Lin, “ESD-protected wideband CMOS LNAs using modified resistive feedback techniques with chip-on-board packaging,” IEEE Trans.
Microw. Theory Tech., vol. 56, no. 8, pp. 1817-1826, Aug. 2008.
[54] Y. Cao, V. Issakov, and M. Tiebout, “A 2kV ESD-protected 18GHz LNA with 4dB NF in 0.13μm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp.
194-195.
[55] A. Wang, On-Chip ESD Protection for Integrated Circuits. Kluwer, 2002.
[56] M.-D. Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang, “ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications,”
IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1194-1199, Aug. 2000.
[57] Y.-W. Hsiao and M.-D. Ker, “An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process,” in Proc. Custom Integrated Circuits Conf., 2008, pp.
233-236.
[58] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J.
Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997.
[59] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 2, pp. 235-249, Jun. 2005.
[60] W. Soldner, M.-J. Kim, M. Streibl, H. Gossner, T. Lee, and D. Schmitt-Landsiedel, “A 10GHz broadband amplifier with bootstrapped 2kV ESD protection,” in IEEE Int.
Solid-State Circuits Conf. Dig. Tech. papers, 2007, pp. 550-551.
[61] M.-D. Ker and C.-Y. Lin, “Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp. 1286-1294, May 2008.
[62] M.-D. Ker and C.-Y. Wu, “Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method-Part I: theoretical derivation,” IEEE Trans. Electron Devices, vol. 42, no. 6, pp. 1141-1148, Jun. 1995.
[63] Y. Zhou, J. Hajjar, A. Righter, and K. Lisiak, “Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models,” in Proc. EOS/ESD Symp., 2007, pp. 175-184.
[64] P. Juliano and E. Rosenbaum, “A novel SCR macromodel for ESD circuit simulation,”
in IEDM Tech. Dig., 2001, pp. 319-322.
[65] M. Natarajan, D. Linten, S. Thijs, P. Jansen, D. Tremouilles, W. Jeamsaksiri, T. Nakaie, M. Sawada, T. Hasebe, S. Decoutere, and G. Groeseneken, “RFCMOS ESD protection and reliability,” in Proc. IEEE Int. Symp. Physical and Failure Analysis of Integrated Circuits (IPFA), 2005, pp. 59-66.
[66] M.-D. Ker and C.-M. Lee, “ESD protection design for giga-Hz RF CMOS LNA with novel impedance-isolation technique,” in Proc. EOS/ESD Symp., 2003, pp. 204-213.
SCR NMOS and low capacitance ESD protection device for self-protection scheme and RF application,” in Proc. IEEE Custom Integrated Circuits Conf., 2002, pp. 93-96.
[68] K. Higashi, A. Adan, M. Fukumi, N. Tanba, T. Yoshimasu, and M. Hayashi, “ESD protection of RF circuits in standard CMOS process,” in RFIC Symp. Dig., Jun. 2002, pp. 31-34.
[69] M.-D. Ker and K.-H. Lin, “ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology,” IEEE J.
Solid-State Circuits, vol. 40, no. 11, pp. 2329-2338, Nov. 2005.
[70] W. Wu, S. Lam, and M. Chan, “Effects of layout methods of RFCMOS on noise performance,” IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2753-2759, Dec.
2005.
[71] S. Dabral and K. Seshan, “Diode and transistor design for high speed I/O,” US Patent 7012304, Mar. 2006.
[72] D. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998.
[73] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2004.
[74] B. Ballweber, R. Gupta, and D. Allstot, “A fully integrated 0.5-5.5 GHz CMOS distributed amplifier,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 231-239, Feb.
2000.
[75] J. Li, S. Joshi, R. Barnes, and E. Rosenbaum, “Compact modeling of on-chip ESD protection devices using Verilog-A”, IEEE Trans. Computer-Aided Design Integrated Circuits Systems, vol. 25, no. 6, pp. 1047-1063, Jun. 2006.
[76] V. Vassilev, G. Groeseneken, S. Jenei, R. Venegas, M. Steyaert, H. Maes, “Modelling and extraction of RF performance parameters of CMOS electrostatic discharge protection devices,” in Proc. EOS/ESD Symp., 2002, pp. 111-118.
[77] K. Chong and Y. Xie, “Low capacitance and high isolation bond pad for high-frequency RFICs,” IEEE Electron Device Lett., vol. 26, no. 10, pp. 746-748, Oct. 2005.
[78] M.-D. Ker, H.-C. Jiang, and C.-Y. Chang, “Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology,” IEEE Trans. Electron Devices, vol.
48, no. 12, pp. 2953-2956, Dec. 2001.
[79] S. Lam, P. Mok, P. Ko, and M. Chan, “High-isolation bonding pad design for silicon RFIC up to 20 GHz,” IEEE Electron Device Lett., vol. 24, no. 9, pp. 601-603, Sep.
2003.
[80] Y.-W. Hsiao and M.-D. Ker, “Bond pad design with low capacitance in CMOS
technology for RF applications,” IEEE Electron Device Lett., vol. 28, no. 1, pp. 68-70, Jan. 2007.
[81] T. Cheung and J. Long, “Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits,” IEEE J. Solid-State Circuits, vol.
41, no. 5, pp. 1183-1200, May 2006.
[82] D. Seo, H. Dabag, Y. Guo, M. Mishra, and G. McAllister, “High-voltage-tolerant analog circuits design in deep-submicrometer CMOS technologies,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 54, no. 10, pp. 2159-2166, Oct. 2007.
[83] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 53, no. 9, pp. 1934-1945, Sep. 2006.
[84] B. Serneels, T. Piessens, M. Steyaert, and W. Dehaene, “A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp.
576- 583, Mar. 2005.
[85] T. Suzuki, M. Kojima, J. Iwahori, T. Morita, N. Isomura, K. Hashimoto, and N. Yokota,
“A study of ESD robustness of cascoded NMOS driver,” in Proc. EOS/ESD Symp., 2007, pp. 403-407.
[86] T. Tang, S. Chen, S. Liu, M. Lee, C. Liu, M. Wang, and M. Jeng, “ESD protection for the tolerant I/O circuits using PESD implantation,” J. Electrostatics, vol. 54, no. 3-4, pp.
293-300, Mar. 2002.
[87] W. Anderson and B. Krakauer, “ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration,” in Proc. EOS/ESD Symp., 1998, pp.
54-62.
[88] M.-D. Ker and W.-J. Chang, “ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers,” IEEE Trans.
Electron Devices, vol. 55, no. 6, pp. 1409-1416, Jun. 2008.
[89] L. Avery, “ESD protection for overvoltage friendly input/output circuits,” U.S. Patent 5708550, Jan. 1998.
[90] M.-D. Ker and C.-T. Wang, “Design of high-voltage-tolerant ESD protection circuit in low-voltage CMOS processes,” IEEE Trans. Device Mater. Reliab., vol. 9, no. 1, pp.
49-58, Mar. 2009.
[91] S. Poon and T. Maloney, “New considerations for MOSFET power clamps,” in Proc.
EOS/ESD Symp., 2002, pp. 1-5.
mixed-voltage I/O in low-voltage thin-oxide CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2006, pp. 546-547.
[93] C.-T. Wang and M.-D. Ker, “Design of power-rail ESD clamp circuit with ultra-low standby leakage current in nanoscale CMOS technology,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 956-964, Mar. 2009.
[94] Y. Lin, C. Wu, C. Chang, R. Yang, W. Chen, J. Liaw, and C. Diaz, “Leakage scaling in deep submicron CMOS for SoC,” IEEE Trans. Electron Devices, vol. 49, no. 6, pp.
1034-1041, Jun. 2002.
[95] S.-H. Chen and M.-D. Ker, “Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology,” IEEE J.
Solid-State Circuits, vol. 42, no. 5, pp. 1158-1168, May 2007.
Vita
姓 名：林群祐 (Chun-Yu Lin) 性 別：男
出生日期：民國 73 年 7 月 28 日 出 生 地：花蓮市
住 址：花蓮市光復街 18-1 號
學 歷：國立交通大學電子工程學系畢業 (91 年 9 月–95 年 1 月) 國立交通大學電子研究所碩士班 (95 年 2 月–95 年 8 月) 國立交通大學電子研究所博士班 (95 年 9 月入學)
論文名稱：全金屬矽化物互補式金氧半製程之矽控整流器及其在射頻電路 之靜電放電防護設計與應用
SCR-Based ESD Protection Designs for Radio-Frequency Integrated Circuits in Fully Silicided CMOS Process