Plasma process induced damage in sputtered TiN metal gate capacitors with ultra-thin nitrided oxide

-

_{Plasma Process Induced Damage in Sputtered TiN Metal Gate Capacitors}

with Ultra-Thin Nitrided Oxide

C.-C. Chen', H.-C. Lin2, C.-Y Chang',

T.-S.

Chao2, S.-C. Huang', W.-E Wu2,

T.-Y.

HuanglV2

and

M.-S. Liang3

'Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. 2National Nan0 Device Laboratories, 1001 Ta-Hsueh Rd., Hsinchu 300, Taiwan, R.O.C.

3Taiwan Semiconductor Manufacturing Co. Ltd., Science-based Industrial Park., Hsinchu 300, Taiwan, R.O.C.

ABSTRACT

A comprehensive study on plasma process induced damage (P2ID) in sputtered TiN metal-gated devices with 4nm N20-nitrided oxide was performed. It is observed that the post-deposition RTA temperature affects both the flat-band voltage (Vfb) and interface state density (Dit). The TiN metal-gated devices also show

a

8 A reduction in the effective oxide thickness,

due to physical damage caused by sputtering and/or oxide consumption during the post annealing step. Finally, degradation in gate oxide integrity caused by severe charging damage during the additional plasma processes in the TiN metal gate process flow is also observed. The P2ID leads to significant degradation in charge-to-breakdown and gate leakage current increase, even for the genuinely robust nitrided oxide used in this study. Finally, N2 plasma post-treatment is found to be effective in suppressing the gate leakage current.

INTRODUCTION

As CMOS technology scales toward sub-0.1 pm regime, the poly gate depletion effect, caused by insufficient dopant activation near the poly/SiO2 interface, becomes increasingly non-tolerable. Due to the voltage drop across the poly depletion layer, an effectively lower surface electric field causes a significant inversion capacitance degradation, which in turn reduces the device driving capability [ 11. This undesirable effect becomes even more severe for advanced devices accompanied by lower thermal budget. To overcome this problem, the

replacement of conventional poly-Si gate by refractory metals, such as TiN or WN, has recently been proposed

[2]-[5]. By employing the metal gate, the gate depletion problem can theoretically be completely eliminated.

treatment is studied to suppress the gate leakage current.

EXPERIMENTAL

MOS capacitors with sputtered TiN gate electrode were fabricated on p-type Si wafers. Capacitors with the conventional n+ poly-Si gate were also processed to serve as the control. The key process flow and the experimental splits are illustrated in Fig. 1. Briefly, a 4nm-thick nitrided oxide was thermally grown in a dry N20/N2 furnace ambient at 900

'C,

followed by the deposition of gate materials. A 200nm-thick TiN film deposited by the reactive ion sputtering with Ar and N2 gas mixture was used for the metal-gate devices, while the control split received the conventional n+ poly-Si gate. This was followed by gate patterning and definition. For the split with TiN gate, the TiN layer was etched in a C12-based helicon-type plasma etcher, followed by photoresist stripping in a down-stream O2 plasma asher. After gate definition, the metal-gate devices were further split to receive rapid thermal annealing (RTA) at three temperatures (i.e., 500

'C,

600

'C,

700

'C)

for 30 sec. While the poly-gate control devices received a standard RTA at 1050

"C

for 30 sec. Afterwards, a 550 nm-thick interlayer dielectric was deposited by LFTEOS and

PETEOS for poly-gate and metal-gate devices,

respectively. Contact holes and metal pads with various antenna area ratios (AAR) were subsequently formed. Finally, a forming gas annealing at 400

'C

was performed. Some of the TiN-gated devices received an additional plasma post-treatment in N2, NO2, or NH3.

RESULTS AND DISCUSSION

2000 5th International Symposium on Plasma Process-Induced Damage. May

RTA temperature, as shown in Fig. 3. Vfb becomes more Plasma-induced charging damage was analyzed by Qbd negative as RTA temperature increases and the spread and gate leakage current (Ig) measurements on devices becomes larger at higher temperatures. In addition, the with various antenna area ratios (AAR). As shown in Fig. mid-gap interface state density (Dit) is also larger (close 7, Qbd as a function of cell position for devices with to 1012 cm-2) for devices at 600 and 700

oca

various AAR indicates that severe charging damage Such phenomenon is believed to be related to the change occurs at the wafer center, consistent with our previous the XRD spectra of T ~ N films after RTA F~~ Moreover, a much more severe damage is observed for TiN-gated devices, since essentially all the devices with

the 700 "C-annealed sample, co-existence of TiN(111) AAR of 10 K me broken down heady, with the

could lead to flat-band voltage shift and a wider spread, edge. ~ i8 further confirms that Severe ~ . QM degradation consistent with previous report [5,6]. Sheet resistance is induced in TiN-gated devices even with a small AAR.

in Table I. Rsh decreases as RTA temperature increases, as shown in ~ i9 and ~~ . i10. ~Large gate leakage . which is ascribed to the grain size increase with current is observed for antenna devices located at the temperature9 consistent with the AFM Observation (data wafer center, despite the fact that our previous experience not shown). However, surface roughness is also found to has shown that N20-nitrided oxide to that used in

increase with RTA temperature* we have performed this study should be genuinely robust to gate leakage SIMS analysis, and the results (data not shown) indicate current degradation caused by plasma charging [71. n i s that higher RTA temperature leads to more Ti finding strongly suggests that plasma charging damage penetration, which could degrade the gate oxide integrity. will be a major reliability for metal gate devices, Stress release during annealing is also a possible reason and a tighter antenna circuit design rule may be

for the observed Dit increase. _{necessary for devices employing metal gate. More efforts}

in Tfi texture and material properties. Figure 4 shows results on capacitors with conventional Poly gate

VI.

and TiN(200) is indeed &served. The texture change exception of those few which are located at the wafer

(Rsh) of TiN also varies with RTA temperature, as listed Similar results are @so observed for Ig measured at -2 V,

11. Plasma Damage in devices with TiN metal-gate

Due to the incompatibility of metal gate with charging damage encountered in metal gate devices. need to be made to fully understand and minimize the conventional processing, metal gate devices may receive lII. ~~~~~~~~i~~ of plasma damage by plasma

additional plasma processing steps, compared to the

conventional poly gate devices. As illustrated in Fig.1, in Plasma passivation, which provides a low temperature addition to the sputter deposition, TiN-gated capacitors

the down-stream

o2

asher, and an additional plasma device reliability in thin film transistor technology grown cumulative plasma char@ng damage is expected to be plasma treatment in an effort to passivate the excessive gate current versus voltage characteristics of capacitors Order Of ma@tude larger than that Of poly gate devices, D~~ to the oxide thinning effect, TiN-gated characteristics, some of the TiN-gated capacitors were than the poly gate counterpart. It is worthy to note here NH3, N 2 0 or N2 at 250 "C for 40 min. This plasma post- that we have also fabricated TiN-gated capacitors with treatment was performed after forming gas annealing. pure O2 gate oxide, and these devices depict significantly Gate leakage current characteristics are depicted in Fig.

worse leakage current characteristics (data not shown) 11. It can be

seen

that significant gate leakage current than the metal-gated devices with nitrided oxide. This reduction is achieved for devices that received N2 plasma trend is consistent with our previous observation that the post-treatment. The leakage current spread is also nitrided oxide is genuinely more robust to plasma improved after plasma treatment. However, for devices damage than the pure oxide [7]. However, gate oxide that received NH3 plasma treatment, gate current increase reliability is also found to be degraded for TiN-gated is observed. The mechanism responsible for this devices even

with

nitrided oxide, as shown in Fig. 6. unexpected degradation is still not clear at this stage, and Significant charge-to-breakdown (Qbd) degradation is could presumably be related to the excessive amount of observed for TiN-gated devices, compared to the poly hydrogen incorporation. On the other hand, N2 plasma gate controls. This can be attributed to the sputter treatment is expected to incorporate nitrogen into the gate damage as well as the mechanical stress caused by dielectric. The formation of strong Si-N bonds in place of thermal coefficient difference between TiN layer and the strained Si-0 bonds and weak Si-H bonds enhance the oxide. Such stress can be minimized by process interface hardness, resulting in the suppression of low- optimization such as reduced TiN thickness, lower RTA level gate current which is dominated by excessive trap- ' temperature, and reduced temperature ramping rate, etc. assisted tunneling. Hence, N2 plasma post-treatment

received two extra plasma ashing steps (i.e., one after (below 300

'c)

and gate definition and the other after contact hole etching) in trapping

deposition step (i.e., PEmOS). As a result, the on glass substrate- In this study, we have also

more pronounced in metal gate devices. Figure 5 shows trap density of TiN-gated devices, which is almost an with both TiN metal gate and the conventional poly gate. as shown PreviouslY in Fig. 3. To improve its capacitor exhibits more Severe leakage characteristics further subjected to an additional plasma post-treatment in effective method to anneal Out

adopted for improving the has been

appears to be an effective method to suppress the gate leakage current for devices employing sputtered TiN metal gate.

CONCLUSION

A comprehensive study on plasma process induced damage in sputtered TiN metal gate devices with 4nm N20-nitrided oxide was reported for the first time. A?

effective oxide thickness reduction by as much as 8 A was found on the metal-gated devices, due probably to physical damage caused by sputtering andor oxide reaction with TiN. Moreover, severe charging damage due to additional plasma processing required for metal gate process integration also results in significant charge-to- breakdown degradation and gate leakage increase for the devices with sputtered TiN metal gate, despite the use of the nitrided oxide known to be genuinely robust to plasma charging damage. Finally, an N2 plasma post-treatment is proposed to effectively suppress the gate leakage current in TiN-gated devices.

ACKNOWLEDGMENT

This work was supported by the National Science Council of the Republic of China under contract No.

REFERENCES

NSC-89-2215-E-3 17-002.

[ l ] B.Yu, etal., Symp. VLSI Tech., 1997, p. 105. [2] H. Yang, etal., IEEEAEDM, 1997, p. 459. [3] B. Maiti, et al., IEEBIEDM, 1998, p. 781.

[4] J. C. Hu, et al., IEEUIEDM, 1997, p. 825.

[5] A. Yagishita, et al., IEEHIEDM, 1998, p. 785. [6] K. Nakajima, etal., Symp. VLSITech., 1999, p. 95. [7] C.-C. Chen, et al., IEEE/EDL, 2000, p. 15.

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L P C V D P o l y , 2 0 0 n m P V D T I N , 2 0 0 n m - Open: Dit - - Solid: Vfb - I I I I

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G a t e D e f i n i t i o n

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I

T h e r m a l 0 , P R A s h i n g 0 , P l a s m a P R A s h i n g

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R T A 1 0 5 0 OC 2 0 s + FA 8 0 0 ° C 2Omin R T A S p l i t s , 30s ( 5 0 0 , 6 0 0 , 70OoC) L P C V D T E O S , 5 5 0 n m P E C V D T E O S , 5 5 0 n m

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T h e r m a 0 , P R A s h i n g , 0 , P l a s m a P R A s h i n g

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I- 8 0 7 0 60 -1.5 -1.0 -0.5 0 . 0 0.5 1 .O 1.5 V g (TiN g a t e ) & V g - h V f b (poly g a t e )

Fig. 2 C-V curves of TiN- and poly-gated devices.

10"

::::

E

€ 5 2 -0.4 5 -0.5

9

-0.6 3 -0.7 > -0.9

Table I Sheet resistance and surface roughness from

AFM of TiN under various RTA temperatures.

~RTA 500 OC+JRTA 600 OC+~RTA 700 oc+

7.4? 0.2- I 6 . e 0.70 I 5.9k 0 . 1 ~

Fig. 1 Key process flow of TiN- and poly-gated devices.

f i h n e s s (n& 0295. I 0.689d I 0.86- I

0 -1 -2 -3 -4 -5 -6 -7 Gate Voltage (volt)

Fig. 5 Gate current characteristics of TiN- and poly- gated devices. h 99 99.9

s

p

90

-

.-

2

70 50 2 30

.-

*

-

_{a 10}

5

u 1 0.1 1 0 ' 100 1 0' 1 0 2 Charge-to-Breakdown (C/cm2)

Fig. 6 Cumulative failure of constant current Qbd tests for TiN- and poly-gated devices under gate iniection polarity.

100

- Poly Gate (a)

99 90 70 5 0 30 1 0 1 - -4 -3 -2 -1 0 1 2 3 4 Cell Index (#)

Fig. 7 Qbd characteristics of (a)poly- and (b)TiN-gated antenna devices as a function of cell position from center.

-

-

-

-

-

-

Area=400 pm 0.1 1 10 1 (RTA 7 0 0 % ) 3 IO Charge-to-Breakdown (C/cm*)

Fig. 8 Cumulative failure of Qbd tests for poly- and TiN-gated devices with various AAR.

106 t

i Open: Poly Gate 0 AAR=16

Solid: TIN Gate (RTA 70OoC) AAR=1 K AAR=lOK 8 c)

3

IO' 100 -4 -3 -2 -1 0 1 2 3 4 Cell Index (#)

Fig. 9 Ig of poly- and TiN-gated devices with various AAR as a function of cell position.

99.9 1 _{I i A} Open: Poly G a t e Solid: TIN G a t e Area 400 j" " 1 0.1 ' ' ' I 6 8 10 20 40 60 80 100 2 Gate L e a k a g e C u r r e n t @ - Z J V ( P A )

Fig. 11 Ig characteristics after plasma treatments.