342 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 7, JULY 2001
ESD Protection Under Grounded-Up Bond Pads in
0.13
m Eight-Level Copper Metal, Fluorinated
Silicate Glass Low-
k Intermetal Dielectric CMOS
Process Technology
Kuo-Yu Chou and Ming-Jer Chen, Senior Member, IEEE
Abstract—Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 m full eight-level copper metal CMOS process technology with fluori-nated silicate glass (FSG) low- intermetal dielectric (IMD). The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point( 2 2). High
current – measured from the different level metal layers stack structures shows that 1) 2 depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) 2 increases with the number of metal layers. The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device. Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications.
Index Terms—Copper metal, die cracking, ESD, fluorinated sili-cate glass, FSG, IMD, intermetal dielectric, low- , stress mismatch, wire bonding.
I. INTRODUCTION
A
GGRESSIVELY scaled CMOS technologies have signifi-cantly driven integrated circuits design toward high-speed and high-performance applications. Owing to requirements for protection of internal circuits during handling and packaging, however, there exists a bottleneck around the I/O pads that ESD protection circuits can not be scaled proportionally as internal ones. Consequently, from generation to generation the tradi-tional ESD protection circuits continue occupying a relatively large I/O region, and such area consumption significantly in-creases with increased growth of high pin count. Even a large area I/O pad itself can severely deteriorate the performance ofManuscript received March 7, 2001; revised April 9, 2001. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract 89-2215-009-049. The review of this letter was arranged by Editor S. Kawa-mura.
K.-Y. Chou was with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. He is now with Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).
M.-J. Chen is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).
Publisher Item Identifier S 0741-3106(01)05419-2.
Fig. 1. SEM image of cross section of (a) a full eight-level metal I/O bond pad and (b) a six-level metal, metal-3 to metal-8, grounded-up bond pad.
the high-speed circuits. To alleviate these problems, moving ESD protection circuits under the bond pads seems to be a so-lution [1], as long as the manufacturability and reliability issues involved are met in advance: cracks due to bonding mechan-ical stress and thermal stress mismatch, induced device degra-dations, etc. The effectiveness of such solution is demonstrated in this paper in a 0.13 m full eight-layer Cu metal/FSG low-intermetal dielectric (IMD) CMOS process technology [2].
II. EXPERIMENTAL
A 0.13 m full eight-layer Cu metal/FSG low- IMD CMOS process technology [2] can offer different combinations of metal layers such as a full eight levels metal bond pad and a single level metal band pad. The ESD protection device in this study was simple 4 shunted 2 cascaded NMOS transistors each with W/L = 15 m/0.4 m. The bond pad size was 70 m 70 m. Fig. 1(a) shows SEM image of cross section of the eight-level metal I/O
CHOU AND CHEN: ESD PROTECTION UNDER GROUNDED-UP BOND PADS 343
Fig. 2. I–V curves of the seven different structures obtained by TLP.
bond pad and Fig. 1(b) that of the six-level metal, metal-3 to metal-8, grounded-up I/O bond pad. A series of test structures were fabricated: 1) the ESD protection device with no band pad above, which is connected to a nearby conventional full eight levels metal bond pad, as schematically depicted in the inset of Fig. 2 for configuration (a); and 2) the ESD protection devices each under different metal stacks structures of the grounded-up bond pads, as all drawn for configuration (b) to (g) in the inset of Fig. 2. 12 kÅ Al metal film was deposited on 10 kÅ Cu top metal pad for Al wedge wire bonding with 100-mW bonding power and 20-g bonding force. Transmission line pulsing (TLP) technique with 100-ns pulse width was performed on the assem-bled test chips to build high current – from which the second breakdown trigger current , a measure of ESD robustness, and the second breakdown trigger voltage can all be gotten.
III. RESULTS ANDDISCUSSION
During Al wedge wire bonding, the ESD protection device under the bond pad experienced a high bonding power and force, then followed by SEM for physical inspection. No cracking phe-nomenon of the bond pad and the underlying IMD layers was found, as displayed in Fig. 1(b), relative to a full eight-level metal I/O bond pad in Fig. 1(a). In TLP experiment, a current pulse generated by discharging a charged transmission line was forced to enter into the device under test. By monitoring the cur-rent flowing through and the voltage on the pad, a high curcur-rent
– point was gotten; and adjusting current pulse height created more such points as shown in Fig. 2 for all structures. The – line (below the second breakdown trigger point) of structure F quite matches that of the conventional one [i.e., ESD protection device with no bond pad above as shown in configuration (a)], and even their second breakdown trigger points are very close to each other. This apparently evidences that the bonding power and force produces no change in the underlying lateral bipolar snapback high current properties.
Further analyzes point out that 1) depends very weakly on metal layers used and 2) increases with the number of metal layers. Thus, the constant is solely determined by the underlying protection device, regardless of pad structures used; and the certain junction power dissipation criterion can serve as the origin of such relationship. As for relatively significant dependencies of , it does not mean that the ESD protection device under the bond pad would be degraded. The mechanism responsible is the presence of the dynamic impedance of the metal layer stacks bond pad structures, and more metal layers yield more impedance values. Taking the equivalent RC circuit model of I/O bond pads into account, the impedance of a spec-ified grounded-up I/O bond pad, , can be written as
344 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 7, JULY 2001
Fig. 3. MeasuredV versus calculated impedance for structure A to F.
where is the level metal resistance, is the ca-pacitance between two metal layers, and the current pulse width is 100 ns in the work. The resulting impedance values are very low, ranging from 0.02 to 2.27 . Fig. 3 displays the measured versus calculated impedance for structure A to F. Strikingly, a linear relationship is built between the two. In particular, the slope and intercept of the line provides relevant information for the underlying ESD protection devices: the intrinsic second breakdown trigger current ( 1.04 A) and voltage ( 7.14 V). Since , a measure of ESD robust ability, shows weak dependency on bond pads, structure A to F features comparable ESD immunity each other. This indicates that moving ESD pro-tection circuits under the bond pads proves reliable in our work. Therefore, it is argued that not only the traditional area con-sumption can be avoided, but also design constraints for I/O
pads can be substantially relaxed. This enables much more flex-ible and robust ESD schemes such as a distributed ESD protec-tion one [3]. Promising potential can be further expected in the microprocessor and ASIC applications where high-level ESD protection is essential [4].
IV. CONCLUSION
The ESD protection devices under the grounded-up bond pads have been successfully realized in 0.13 m full eight-level Copper metal/FSG low- IMD CMOS technology. The under-lying mechanism has been clarified and the promising potential has been projected. The impact of other parameters such as metal thickness or metal linewidth on the ESD performances, which would provide practical condition for reliability and manufacturability issues, will be further researched.
ACKNOWLEDGMENT
The authors would like to thank R&D/TSMC engineers for their assistance with manufacturing wafers, and QA/TSMC per-sonnel for packaging support.
REFERENCES
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