行政院國家科學委員會專題研究計畫 成果報告
次 32 奈米多重閘極元件的特性分析與模式建立-變異性與
微縮性，高頻類比特性，以及介觀現象的探討
研究成果報告(精簡版)
計 畫 類 別 ： 個別型 計 畫 編 號 ： NSC 97-2221-E-009-162- 執 行 期 間 ： 97 年 08 月 01 日至 98 年 07 月 31 日 執 行 單 位 ： 國立交通大學電子工程學系及電子研究所 計 畫 主 持 人 ： 蘇彬 計畫參與人員： 博士班研究生-兼任助理人員：李維 博士班研究生-兼任助理人員：吳育昇 博士班研究生-兼任助理人員：郭俊延 博士班研究生-兼任助理人員：胡璧合 博士班研究生-兼任助理人員：范銘隆 報 告 附 件 ： 出席國際會議研究心得報告及發表論文 處 理 方 式 ： 本計畫可公開查詢中 華 民 國 98 年 10 月 26 日
行政院國家科學委員會補助專題研究計畫
■ 成 果 報 告
□期中進度報告
次 32 奈米多重閘極元件的特性分析與模式建立
計畫類別：■ 個別型計畫
□ 整合型計畫
計畫編號：NSC
97-2221-E-009-162
執行期間：
97 年
08 月
01 日至
98
年
07 月
31 日
計畫主持人：蘇彬
計畫參與人員：李維、吳育昇、郭俊延、胡璧合、范銘隆
成果報告類型(依經費核定清單規定繳交)：■精簡報告
□完整報告
本成果報告包括以下應繳交之附件：
□赴國外出差或研習心得報告一份
□赴大陸地區出差或研習心得報告一份
■出席國際學術會議心得報告及發表之論文各一份
□國際合作研究計畫國外研究報告書一份
處理方式：除產學合作研究計畫、提升產業技術及人才培育研究計畫、
列管計畫及下列情形者外，得立即公開查詢
□涉及專利或其他智慧財產權，□一年□二年後可公開查詢
執行單位：國立交通大學電子工程學系
中
華
民
國
98
年
07
月
31
日
次 32 奈米多重閘極元件的特性分析與模式建立
Investigation and Modeling of Sub-32 nm Multiple-Gate SOI CMOS
計畫編號 : NSC 97-2221-E-009-162
執行期限 : 97 年 08 月 01 日 至 98 年 07 月 31 日
主持人 : 蘇彬
國立交通大學電子工程學系
一、中文摘要 在本計畫中我們對次 32 奈米多重閘極 SOI CMOS 的元件特性作深入研究與模式建 立。由於傳統 CMOS 在次 32 奈米製程的困 難日增，多重閘極 SOI CMOS 元件提供了一 種有利於 CMOS 微縮的解決之道。在本計畫 中我們對 Schrodinger 方程式考慮短通道 元件的位能井，利用求得的解析解來預測 短通道環閘極(Gate-All-Around)元件的量 子侷限效應。此外，針對多重閘極元件， 在 56K 至 300K 溫度範圍間，比較並分析載 子傳輸在重疊與非重疊閘源(汲)極結構中 的差異。本計畫對次 32 奈米多重閘極元件 所發展的元件模型，不僅對使用此前瞻技 術的電路設計極為重要，也有益於此前瞻 元件設計的最佳化。 關鍵詞 : SOI CMOS，多重閘極，元件設計，電路設 計，元件模型，載子傳輸，重疊/非重疊閘 源(汲)極，量子侷限效應，奈米電子 AbstractIn this project we have conducted investigation and modeling of sub-32nm multiple-gate SOI CMOS. We have proposed an analytical model considering quantum confinement effects in short-channel gate-all-around MOSFETs under subthreshold region. In addition, we have conducted a comparative study of carrier transport characteristics for multi-gate FinFET MOSFETs with and without the nonoverlapped source/drain structure. Our study will be instrumental for
ultra-scaled multi-gate device/circuit designs.
Keywords :
SOI CMOS, multiple gate, nanowire, device design, carrier transport, nonoverlapped, overlapped, quantum confinement, silicon nanoelectronics
二、計畫目的及研究方法
As the semiconductor industry is confronted with the difficulty of downsizing the transistor dimension, multiple-gate SOI is emerging as an important device structure for CMOS scaling [1]. In this project, we have conducted investigation and modeling for sub-32nm multi-gate SOI CMOS. This report describes our two main tasks regarding multi-gate research during this project:
Task I: Analytical Quantum Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold Region [9]
Task II: A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate SOI MOSFETs [23]
Task I
Gate-All-Around (GAA) MOSFET is an ideal structure to provide superior electrostatic behavior and is recognized as an important candidate for ultimate CMOS scaling [2]-[4]. As the channel thickness of GAA MOSFETs scales down, the quantum confinement effects become significant. This two-dimensional confinement effect is often considered to be independent of the carrier flow direction (i.e., channel length direction). Thus, the quantum
confinement model for long-channel and undoped cylindrical GAA MOSFETs was proposed using the flat well approximation [4], [5]. For short-channel devices, however, the center of the potential well is altered by the source/drain coupling due to the short channel effect and the flat well approximation is no
longer valid. An accurate quantum
confinement model considering the short channel effects is crucial to GAA MOSFET design.
In this work, an analytical solution of Schrödinger equation for short-channel GAA MOSFET under the subthreshold region is proposed. The subthreshold behaviors represent the device electrostatic integrity that is important for ultra-scaled device design. Besides the lightly-doped GAA MOSFETs, our analytical model can also be used for heavily-doped devices.
Task II
Multi-gate silicon-on-insulator (SOI) MOSFET (MuGFET) structures provide superior electrostatic integrity needed for MOSFET scaling entering the deca- to nanometer regime [1]. For MuGFET device design, source/drain engineering is crucial because of the parasitic drain/source resistance [6] and the parasitic fringing/overlap capacitance that may limit circuit performance [7]. Two options in the source/drain engineering are the overlapped structure with light-doping-drain/source (LDD/LDS) and the nonoverlapped structure. Whether the various source/drain engineering will impact the carrier transport in nanoscale MuGFETs merits examination.
In this work, we conduct a systematic comparison of carrier transport between overlapped and nonoverlapped multi-gate SOI MOSFETs. The investigation has included measurements from T = 300 K to 56 K.
三、結果與討論
1. Analytical Quantum Confinement Model
for Short-Channel Gate-All-Around
MOSFETs Under Subthreshold Region [9]
Fig. 1 shows a schematic sketch of the GAA MOSFET structure. The eigen-energy and eigen-function of channel carriers are crucial to the quantum confinement effect, and they can be determined by solving the Schrödinger equation. The conduction band edge needed in the Schrödinger equation can be obtained from the channel potential solution of Poisson’s equation.We have derived the channel potential solution for GAA MOSFETs in the subthreshold region [8], and the verification with the TCAD simulation is shown in Fig. 2. The channel potential solution can be further reduced to the parabolic form to simplify the solution of the Schrödinger equation. Thus, the Schrödinger solutions for short-channel GAA MOSFETs under the subthreshold region can be analytically derived [9]. Using the calculated eigen-energies and eigen-functions, we can calculate the electron density in the channel. The impact of quantized eigen-energies and eigen-functions on the electron density is incorporated into the effective density of states for conduction band [10].
Fig. 3 shows the calculated quantized jth eigen-energy (Ej) and the square of jth
eigen-function (|Ψj|2) for lightly-doped long-channel
GAA devices, and the results are verified with TCAD simulation that numerically solves the self-consistent solution of 3-D Poisson and 2-D Schrödinger equations [11]. It can be seen that Ej and the difference between two distinct
eigen-energies increase with decreasing channel diameter (D). Due to the cylindrical symmetry in theθ direction,theE2 and E3 are
degenerate because they correspond to the states of angular quantum number l = 1 and -1. Similarly, the E4 and E5 are degenerate. The
results in Fig. 3 can also be predicted by the quantum confinement model using the flat
well approximation [4], [5]. For short-channel lightly-doped GAA devices, however, the conduction band edge EC is lowered by
source/drain coupling and is bended from a flat well to a parabolic-like well (Fig. 4). Since the EC is not spatially constant for
short-channel devices, we choose the EC at the
channel center (r = 0) as the reference energy. Fig. 4 shows that the Ej’s can be correctly
predicted by our analytical solution considering the short-channel potential barrier. Fig. 5(a) shows that the lowest eigen-energy (E1) increases as channel length decreases.
This eigen-energy shift results from the bending of EC due to the short channel effect.
Fig. 5(b) shows that the square of lowest eigen-function (|Ψ1|2) for short-channel
lightly-doped device is more centralized to the channel center. This is because the EC barrier
at the channel center (r = 0) is lower than that near the insulator/channel interface (r = D/2), and the electron density becomes larger at r = 0. Fig. 6 shows that the E1 increases with VDS.
In other words, the drain-induced-barrier-lowering (DIBL) increases the ECbending and
affects the quantum confinement effects. Our analytical model can also be used to assess the impact of quantum confinement on heavily-doped GAA MOSFETs. Similar to the lightly-doped short-channel devices, the EC of
heavily-doped devices can be described by the parabolic form. In contrary to the upward bending of ECin the lightly-doped case, the EC
bends downward for heavily-doped devices. Fig. 7 shows that the EC for long-channel
heavily-doped GAA device shapes the potential well near the interface (r = D/2). Therefore, we choose the EC at r = D/2 as the
reference energy for long-channel GAA devices. Fig. 8(a) shows that the E1 of
long-channel GAA devices increases with long-channel doping. This is because as the channel doping increases, the surface electric field increases and hence the bending of ECat the interface is
increased. As a result, the E1 increases due to
the stronger electrical confinement. Besides, it
can be seen that for heavily-doped channel (e.g., 5×1018cm-3), the E1 increases with
increasing channel diameter, which is contrary to the lightly-doped case (e.g., 1×1015cm-3). This is because for heavily-doped devices, the electrical confinement becomes stronger with increasing channel diameter, as shown in Fig. 8(b).
Fig. 9 compares the electron density distribution calculated from the classical model [8] and the quantum confinement model. It can be seen from Fig. 9(a) that for lightly-doped short-channel GAA MOSFET, the electron density near the interface (r = D/2) predicted by the quantum confinement model is smaller than classical model. Fig. 9(b) shows that for heavily-doped long-channel GAA MOSFET, the peak electron density predicted by the quantum confinement model is away from the interface, while the classical model predicts the highest electron density at the interface. Fig. 10 compares the average electron density at y = 0.5Leff calculated from
the classical model and the quantum confinement one for lightly-doped short-channel devices. It can be seen that the discrepancy becomes larger with reducing channel diameter.
In conclusion, we have proposed an analytical model for quantum confinement
effects in GAA MOSFETs under the
subthreshold region. The Schrödinger equation is solved considering the bended potential well of parabolic form. Our analytical model accurately predicts the impact of short-channel effects on the eigen-energy and eigen-function of GAA devices. This short-channel quantum-confinement model is crucial to the ultra-scaled GAA MOSFETs design.
2. A Comparative Study of Carrier
Transport for Overlapped and
Nonoverlapped Multiple-Gate SOI
MOSFETs [23]
Fig. 11(a) shows a schematic view of the multi-gate SOI MOSFET investigated in this study. Note that the LDD/LDS implantation was performed for the overlapped structure [Fig. 11(c)] and was skipped for the nonoverlapped structure [Fig. 11(b)]. In this study, we compare these two types of devices based on the same effective source-drain length Leff.
Current-voltage measurements (IDS−VGS)
at VDS =50mV under T =300K to 56K were
performed for the overlapped device 1 with Wfin = 25nm and Lg = 80nm (Fig. 12) and for
the nonoverlapped device 2 with Wfin= 25 nm
and Lg = 30 nm (Fig. 13). Fig. 12 shows that
the subthreshold swing S for the overlapped device 1 decreases with temperature. We have confirmed that the S–T characteristic follows the Boltzmann law S = n(kBT/q) ln (10) with
the body effect coefficient n ≈1.16. The linear temperature dependence of S is a feature of fully depleted SOI [12] and has also been observed in trigate SOI MOSFETs [13]. For the nonoverlapped device 2, however, the linear temperature dependence of S can only be seen when temperature is higher than 223 K (Fig. 13). For temperature below 223 K, S is constant and does not follow the Boltzmann law. This suggests that for the nonoverlapped device 2, tunneling current dominates the fundamental limitation of leakage current instead of the thermal current [14]. We have noted that similar S behavior has been reported at T < 100 K for the planar nonoverlapped nMOSFET in [14]. It implies that the leakage current associated with thermionic emission is suppressed in our MuGFET. The insensitive temperature dependence of IDS can also be
found in the strong inversion region for the nonoverlapped device 2 (Fig. 13). In contrast to that of the overlapped device 1 (Fig. 12), the
IDS for VGS > 0.6V is nearly independent on
temperature. These results indicate that carrier transport in the strong inversion region is determined by the phonon-limited mobility for the overlapped device 1, but not for the nonoverlapped device 2. To further compare the carrier transport characteristics for overlapped and nonoverlapped devices, we have investigated channel conductance (GDS =
IDS/VDS) with low VDS. Fig. 14 shows the
measured GDS versus VGS characteristics for
the overlapped device 3 with Wfin= 10 nm and
Lg = 60 nm. Significant GDS fluctuations can
be seen at T = 56 K [Fig. 14(a)]. Similar GDS
fluctuations have been reported in [15] and attributed to the intersubband scattering. While the number of populated subbands increases with increasing VGS, the intersubband
scattering also increases with each new subband [16]. In other words, when VGS
increases, the GDS increases due to new
populated subbands and then decreases due to the mobility reduction (i.e., the increase of intersubband scattering). Thus, fluctuations can be seen in the GDS −VGS characteristics.
We have noted that the GDS fluctuations
almost occur at the same VGS, such as the
spike at VGS −VT = 0.425 V [Fig. 14(a)]. We
have also noted that for the wider overlapped devices (i.e., device 1) with negligible subband splitting, the GDSfluctuations can not be found.
For the nonoverlapped device 2 in the high VGS regime, the GDS increases with VDS
and temperature as can be observed in Fig. 15(a) and (b), respectively. Such VDS and
temperature dependence of GDSare completely
opposite to that of the overlapped device 3 (Fig. 14) and cannot be ascribed to the intersubband scattering effect. In addition, Fig. 15 also shows interesting fluctuations with negative differential resistance in the GDS.
Although the GDS fluctuations in Fig. 15 were
observed in the same measurement conditions as Fig. 14, one can safely state that it does not result from the intersubband scattering.
Fig. 16 shows the electronic potential calculated using ISE device simulation [17]
for our nonoverlapped device. The
nonoverlapped gate to source/drain regions act as the voltage-controlled potential barriers along the channel. Therefore, carrier transport from source to drain is significantly influenced by the barriers as illustrated in Fig. 16: directly tunneling (Ia), thermally associated tunneling
(Ib), and thermionic emission (Ic). The
contribution of these three mechanisms to IDS
depends on VGSand temperature. For high VGS,
Iais dominant. With decreasing VGS, increased
electronic potential diminishes Ia and thus Ib
and Icbecome important. In other words, IDSin
the subthreshold region results mainly from Ib
and Icfor the nonoverlapped device. It is worth
noting that carrier transport by Icrequires more
thermal energy and may be suppressed under low temperature. Fig. 17 shows the temperature sensitivity of IDS(Δlog(IDS)/ΔT)
versus VGS characteristics extracted from Figs.
12 and 13 under high and low temperatures. For the nonoverlapped device in the strong inversion region, the insensitive temperature dependence manifests the importance of Ia. On
the other hand, the negative temperature dependence for the overlapped device in the strong inversion region indicates phonon scattering. In addition, it can be noted in Fig. 17(a) that Δlog(IDS)/ΔT significantly increases
with decreasing VGS for both overlapped and
nonoverlapped devices. This suggests that in the high temperature regime the subthreshold current of the nonoverlapped device is dominated by Ic, similar to the overlapped
device. When temperature decreases, however, the thermionic emission Ic is suppressed and
the Ib component with weak temperature
dependence becomes dominant. In other words, the suppression of Ic under low temperature is
the main reason of S saturation for the nonoverlapped device. It should be noted that such mechanism of S saturation is different from lateral tunneling through the channel, as
presented for ultrashort devices in [14] and [18].
Fig. 16 also shows an equivalent quantum well under the gate in the nonoverlapped device [14]. It is worth noting that the height of the voltage-controlled potential barriers in the nonoverlapped regions increases with VGS.
The consequence is the plausibility of electron-wave confined between the barriers. When the length of the quantum well, d, is smaller than the inelastic-scattering (e.g., phonon scattering) length, the phase-coherent electron wavefunction over the entire channel as well as quantum interference between coherent electronwaves occur. The quantum interference enhances the electron backscattering probability [19], [20] and thereby reduces the conductivity expected classically. Such quantum correction to the conductivity is the weak localization effect [19], [20] and logarithmically dependent on temperature as Δσ= (pe2/πh) ln(T), where the value of p depends on the scattering process. When T = 56 K, the carriers at VDS = 50 mV
experience more heating (more phonon scattering) and thus less localization effect than those at VDS = 1 or 2 mV. Therefore, the
GDS measured at VDS = 50 mV is larger than
that at VDS = 1 or 2 mV (Fig. 15). From the
GDS data at VDS = 2 mV under T = 56 K and
223 K in Fig. 15, we can estimate that p ≈ 1, which is close to the results in [21] for the 2-D electron gas in Si MOSFETs.
The quantum-mechanical interference for an electron wave passing through a quantum well also results in oscillating transmission probability. Fig. 18 shows the calculated Trfor
the quantum well in Fig. 16. The values of d and (E −eVp) used in Fig. 18 are based on our
experiments. It is worth noting that the Tr
oscillation becomes obvious with increasing VGS as well as the depth of the quantum well.
From the Tr calculation based on d = 30 nm
and (E −eVp) = 0 −5 meV (Fig. 18), we can
observe three transmission maxima due to constructive interference (i.e., Tr = 1) at VGS≈
0.2, 0.43, and 1 V. When (E −eVp) increases,
we observed smaller Tr oscillations and shifts
in the corresponding transmission maximum. In other words, the electron energy distribution may result in group-like Tr oscillations as
shown in the groups 1–3 of Fig. 18. We found that such group-like fluctuations can also be seen in the G’m (G’m=dGm/dVGS, Gm=
dIDS/dVGS) characteristics in Fig. 19 as well as
in the GDS characteristics shown in Fig. 15(a).
We have noted that nearly every peak in G’m
(Fig. 19) can correspond to the peak in GDS
[Fig. 15(a)]. It is worth noting that the G’m
oscillation of Group 3 is more significant and wider than that of groups 1 and 2, which is consistent with the simulation results in Fig. 18. Remind that both the potential barrier height in Fig. 16 and GDSfluctuations in Figs.
15 and 19 increase with VGS. For devices with
the same size, similar G’m oscillations can also
be observed and have been presented in our previous study [22].
In conclusion, we have conducted a comparative study of carrier transport characteristics for MuGFETs with and without the nonoverlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the nonoverlapped devices, however, we found insensitive temperature dependence of IDS in both subthreshold and
inversion regimes. Our low-temperature measurements indicate that the intersubband scattering is the dominant carrier transport mechanism for narrow overlapped MuGFETs. For the nonoverlapped MuGFETs, the voltage-controlled potential barriers in the nonoverlapped regions may give rise to the weak localization effect (conductance reduction) and the quantum interference fluctuations.
四、計畫成果自評
In this project we have conducted investigation and modeling of sub-32nm multiple-gate SOI CMOS. We have presented an analytical model for quantum confinement effects in short-channel GAA MOSFETs under the subthreshold region. In addition, we have conducted a comparative study of carrier transport characteristics for multi-gate MOSFEs with and without the non-overlapped source/drain structure. Our study will be instrumental for ultra-scaled multi-gate device/circuit designs.
Our essential results for the multi-gate project have been disseminated through research reports in referred journals [9][23][27] and international conference proceedings [24]-[26] as well as used in education of our graduate students to become leading researchers in silicon-based nanoelectronics.
五、參考文獻
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9, pp. 2151-2159, September 2006.
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[13] J.-P. Colinge et al, “Temperatureeffects on trigateSOIMOSFETs,”IEEE EDL., vol.
27, no. 3, pp. 172–174, Mar. 2006.
[14] F. Boeuf et al., “16 nm planarNMOSFET manufacturable within state-of-the-art CMOSprocess thanks to specific design and
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[16]J.-P. Colinge et al., “Room-temperature low-dimensional effects in Pi-Gate SOI MOSFETs,” IEEE EDL., vol. 27, no. 9, pp. 775–777, Sep. 2006.
[17] ISE, Integrated Systems Engineering AG, DESSIS Ref. Manual Release 10.0, 2004. [18] M. Fukuma, “New frontiers of sub-100 nm VLSI technology—Moving toward device
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[22] W. Lee, P. Su et al., “An experimental assessment of quantum interference in multiple-gate SOI nMOSFETs with non-overlapped gate to source/drain structure near room temperature,” Proc. IEEE Silicon
Nanoelectron. Workshop, Kyoto, Japan, June
2007, p. 15.
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IEEE Transactions on Nanotechnology, vol. 8,
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[24] Y. Wu, M. Fan, and P.Su,“Investigation of Switching Time Variations for FinFET and Bulk MOSFETs using the Effective Drive Current Approach,”Proc. IEEE 2009 Silicon
Nanoelectronics Workshop, Kyoto, June 2009,
p. 7.
[25] M. Fan et al., "Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region," Proc. 2009 IEEE International SOI Conference, Foster City,
California USA, October 2009.
[26] Y. Wu and P. Su, "Quantum Confinement Effect in Short-Channel Gate-All-Around MOSFETs and Its Impact on the Sensitivity of Threshold Voltage to Process Variations,"
Conference, Foster City, California USA,
October 2009.
[27] W. Lee and P. Su, "Single-electron effects in non-overlapped multiple-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors," Nanotechnology, vol. 20, no. 6, February 2009.
insulator rv yv D eff L i t θv channel insulator rv yv D eff L i t θv channel
Fig. 1. Schematic sketch of the GAA structure investigated in this study. The origin point (r = 0, y = 0) is defined at the center of the channel/source junction.
0.0 0.2 0.4 0.6 0.8 1.0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 model Na=1x10 15 cm-3 Na=3x1018cm-3
Leff=20nm, Diameter=15nm, EOT=1.5nm
VDS=1.0V, VGS=0.2V r-direction (y=0.5*Leff) po te nt ia l [V ] (r / Diameter+0.5), y / Leff y-direction (r=0) simulation
Fig. 2. Analytical potential distribution of GAA MOSFETs compared with TCAD simulation. A midgap workfunction 4.5eV is used.
4 8 12 16 0.0 0.1 0.2 0.3 0.4 0.5 0.6 symbol: simulation line: model E4(=E5) E2(=E3)
Leff=100nm, 4-fold valley Na=1x1015cm-3, y=0.5*L eff VDS=0.05V, VGS=0V Ej − EC (r = 0 ) [e V] Diameter [nm] E1 (a) -0.5 0.0 0.5 0 1x1013 2x1013 3x1013 4x1013 symbol: simulation line: model |Ψ4|2 +|Ψ5|2 |Ψ 2| 2 +|Ψ3|2 | Ψj | 2 [cm -2 ] r / Diameter
Leff=100nm, D=5nm, 4-fold valley Na=1x1015cm-3, y=0.5*L
eff
|Ψ1|2
(b)
Fig. 3. (a) Quantized eigen-energies for long-channel lightly-doped GAA devices. (b) The square of wavefunctions corresponding to the eigen-energies of GAA device with D=5nm in (a).
-0.5 0.0 0.5 0.20 0.25 0.30 0.35 0.40 0.45 0.50 symbol: simulation line: model
Leff=15nm, D=10nm, 4-fold valley Na=1x1015cm-3, y=0.5*L eff VDS=0.05V, VGS=0V Ene rg y [e V] E 4 E2 E1 EC 10 100 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 D=15nm D=10nm D=8nm symbol: simulation line: model E1 − EC (r =0) [eV ] Leff [nm] 4-fold valley Na=1x1015cm-3, y=0.5*L eff VDS=0.05V,VGS=0V (a) -0.5 0.0 0.5 0.0 2.0x1012 4.0x1012 6.0x1012 8.0x1012 1.0x1013 Leff=100nm Leff=10nm symbol: simulation line: model D=10nm, 4-fold valley Na=1x1015cm-3, y=0.5*L eff VDS=0.05V VGS=0V | Ψ1 | 2 [c m -2 ] r / Diameter (b)
Fig. 5. (a) Channel length dependence of the first eigen-energy for lightly-doped GAA devices with various channel diameter. (b) Comparison of the square of first eigen-function for long-channel and short-channel GAA MOSFETs.
0.0 0.2 0.4 0.6 0.8 0.02 0.03 0.04 0.05 0.06 E1 − EC (r =0 ) [e V] VDS [V] symbol: simulation line: model 4-fold valley Na=1x1015 cm-3 Leff=15nm y=0.5*Leff VGS=0V D=15nm D=10nm D=8nm
Fig. 6. Drain bias dependence of the first eigen-energy of short-channel lightly doped GAA devices with various channel diameter. -0.5 0.0 0.5 0.20 0.25 0.30 0.35 0.40 E4 E2 E1 symbol: simulation line: model
Leff=100nm, D=15nm, 4-fold valley Na=5x10 18 cm-3 , y=0.5*Leff VDS=0.05V, VGS=0V Energy [eV] r / Diameter EC 1015 1016 1017 1018 1019 0.00 0.02 0.04 0.06 0.08 0.10 0.12 D=15nm D=13nm E1 − EC (r = 0.5 *D) [e V] symbol: simulation line: model Leff=100nm, 4-fold valley y=0.5*Leff VDS=0.05V, VGS=0V Doping Concentration [cm-3] D=10nm (a) (b) 0.00 3.25 6.50 0.00 0.03 0.06 0.09 0.120.0 2.5 5.0 7.5 Leff=100nm, Na=5x1018cm-3 y=0.5*Leff VDS=0.05V VGS=0V E1(D=15nm) E1(D=13nm) EC (D=13nm) {EC , E 1 } − EC (r = 0 .5 *D ) [e V ] r [nm] EC (D=15nm) r [nm]
Fig. 8. (a) Impact of channel doping on the first eigen-energies of long-channel GAA devices with various channel diameter. (b) The first eigen-energies and conduction band edges of heavily-doped GAA devices with D = 13nm and D = 15nm, respectively. -0.5 0.0 0.5 1011 1012 1013 1014 1015 1016 QM Leff=15nm, D=10nm Na=1x1015cm-3, y=0.5*Leff VDS=0.05V, VGS=0V symbol: simulation line: model r / Diameter E le c tr on De ns ity [ c m -3] CL (a) -0.5 0.0 0.5 107 108 109 1010 1011 1012 1013 1014 QM Leff=100nm, D=20nm Na=5x1018cm-3, y=0.5*L eff VDS=0.05V, VGS=0V symbol: simulation line: model r / Diameter Electron Dens ity [cm -3 ] CL (b)
Fig. 9. Comparison of electron density distribution between classical model (CL) and quantum confinement model (QM). (a) Lightly-doped short-channel GAA device. (b) Heavily-doped long-channel GAA device.
5 10 15 1011 1012 1013 1014 1015 1016 1017 symbol: simulation line: model Leff=20nm Na=1x1015cm-3, y=0.5*L eff VDS=0.05V, VGS=0V Ave rage El ectron D ensity [c m -3 ] QM CL
Fig 18. Calculated transmission probability Tr
versus VGS for d = 30 nm and E − eVp = 0–5,
5–10, and 10–15 meV.
Fig 19. Measured G’
m/VDS versus (VGS−VT)
characteristics for the nonoverlapped device 2 with Lg
= 30 nm and Wfin = 25 nm at various VDS and
temperature. (G/
m = dGm/dVGS and Gm = dIDS/dVGS).
Fig 17. Measured temperature sensitivity of drain current (Δlog(IDS)/ΔT) versus (VGS−VT)
characteristics for overlapped and nonoverlapped devices under (a) high temperature, T = 300 to 250 K and (b) low temperature, T = 223 to 56 K. Fig 16. Calculated electronic potential for the
nonoverlapped gate to source/drain structure at VGS
= 0V to 1 V. Vp : peak potential value in the
nonoverlapped region. Vc : potential value at the
channel center. E: carrier energy. d: width of the effective quantum well. Ia : direct tunneling
through the potential barrier of the nonoverlapped region. Ib : thermally associated tunneling. Ic :
thermionic emission.
Fig 15. Measured GDS versus (VGS−VT) characteristics
for the nonoverlapped device 2 with Lg = 30 nm and
Wfin = 25 nm at various VDS under (a) T = 56 K and
(b) T = 223 K. Fig 14. Measured channel conductance (GDS) versus
(VGS−VT) characteristics for the overlapped device 3
with Lg = 60 nm and Wfin = 10 nm at various VDS
under (a) T = 56 K and (b) T= 223 K.
Fig 13. Measured IDS versus VGSat VDS= 50 mV
under T = 300 to 56 K for the nonoverlapped FinFET device 2 with Wfin = 25 nm and Lg = 30 nm.
Fig 12. Measured IDSversus VGSat VDS= 50 mV
under T = 300 to 56 K for the overlapped FinFET device 1 with Wfin = 25 nm and Lg = 80 nm.
Fig 11. (a) Multiple-gate FinFET SOI structure investigated in this work and its cross-sectional AA’ view along the channel direction showing (b) nonoverlapped gate to source/drain structure and (c) overlapped gate to source/drain structure. 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 -0.5 0 0.5 1 VGS (V) I DS (A ) 0E+0 1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 9E-6 1E-5 I DS (A ) T=56K T=223K T=250K T=300K
Overlapped FinFET Device 1
Lg=80nm, Wfin=25nm, VDS=50mV 0 20 40 60 80 0 100 200 300 T (K) S (m V/ d e c ) 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 -1 -0.5 0 0.5 1 VGS (V) I DS (A ) 0E+0 1E-6 2E-6 3E-6 4E-6 5E-6 6E-6 7E-6 8E-6 I DS (A ) T=56K T=223K T=250K T=300K
Non-overlapped FinFET Device 2
Lg=30nm, Wfin=25nm, VDS=50mV 0 50 100 150 200 0 100 200 300 T (K) S ( m V/ d e c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.2 0.4 0.6 0.8 VGS-VT (V) Vds=50mV Vds=1mV (b) T = 223K 0 1 2 3 4 0 0.2 0.4 0.6 0.8 VGS-VT (V) G DS (e 2 /h ) Vds=50mV Vds=5mV Vds=1mV (a) T = 56K Overlapped Device 3 Lg=60nm Wfin=10nm (mask-defined) Wfin ~5nm (minimum) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.2 0.4 0.6 0.8 VGS-VT (V) Vds=50mV Vds=2mV (b) T = 223K 0 1 2 3 4 0 0.2 0.4 0.6 0.8 VGS-VT (V) G DS (e 2 /h ) Vds=50mV Vds=2mV Vds=1mV (a) T = 56K Non-overlapped Device 2 Lg=30nm Wfin=25nm eVp eVc d E Ia Ib Ic -0.59 -0.57 -0.55 -0.53 -0.51 -0.49 -0.47 -0.45 0 20 40 60 80 channel direction (nm) El e c tr o n ic Po te n ti a l ( e V) S D G VGS=0~1V -0.002 0 0.002 0.004 0.006 0.008 0.01 -0.4 0 0.4 0.8 VGS-VT(V) (l og( I DS ,T 1 )-log( I DS ,T 2 ))/(T 1 -T 2 ) T1 = 300KT2 = 250K Non-overlapped Overlapped (a) -0.4 0 0.4 0.8 VGS-VT(V) T1 = 223K T2 = 56K Non-overlapped Overlapped
(b) Group 1 Group 2 Group 3
-1.0E-3 -5.0E-4 0.0E+0 5.0E-4 1.0E-3 1.5E-3 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VGS-VT (V) G m '/V DS (S /V 2 ) T=56K, VDS=50mV T=300K, VDS=50mV T=300K, VDS=2mV Non-overlapped Device 2 Lg=30nm Wfin=25nm
出席國際學術會議心得報告
計畫編號 NSC97-2221-E-009-162 計畫名稱次 32 奈米多重閘極元件的特性分析與模式建立
出國人員姓名 服務機關及職稱主持人: 蘇彬
國立交通大學電子工程學系
會議時間地點 June 13-17, 2009 Kyoto, Japan會議名稱 2009 Silicon Nanoelectronics Workshop (June 13-14) 2009 Symposium on VLSI Technology (June 15-17)
發表論文題目
(1) Impact of Uniaxial Strain on Channel Backscattering Characteristics and Drain Current Variation for Nanoscale PMOSFETs (VLSI Symposium) (2) Investigation of Switching Time Variations for FinFET and Bulk MOSFETs
using the Effective Drive Current Approach (Silicon Nanoelectronics
Workshop)
(3) Investigation of Mismatching Properties in Nanoscale MOSFETs with Symmetric/Asymmetric Halo Implant (Silicon Nanoelectronic Workshop)
一、參加會議經過
VLSI Symposium has long been recognized as one of the most important conferences in the VLSI field. This year, a total of 205 papers from 15 countries were submitted, and 82 papers were accepted by the conference. Our paper “Impact of Uniaxial Strain on Channel Backscattering Characteristics and Drain Current Variation for Nanoscale PMOSFETs”was
presented at the Session 6A - Variability on June 16. The chairpersons were Dr. Masahara from AIST, Japan and Prof. T.-J. King from UC Berkeley. In this work, we used a novel generalized temperature-dependent method to examine the impact of uniaxial strain on backscattering characteristics in nanoscale PFETs. We showed that the backscattering coefficient can be reduced by the uniaxially-compressive strain. We further demonstrated that the strain technology can improve the drain current variation as well as the mismatching properties through the enhanced ballistic efficiency. Overall our presentation went pretty well.
Regarding the Silicon Nanoelectronics Workshop, it is one of the major international conferences in the area of nanoelectronics, bridging between the mainstream CMOS
technology and the Si-based nanotechnology. This is the 14thworkshop in series. The program has included 5 invited talks, 24 oral presentations, and 52 poster presentations. Our paper
“Investigation of Switching Time Variations for FinFET and Bulk MOSFETs using the Effective
Drive Current Approach”was oral presented at the Session 1 –Nano MOSFETs in the
effective drive current approach in CMOS inverters. Our study indicated that for bulk MOSFETs, the switching time variation caused by line edge roughness (LER) may be larger than that caused by random dopant fluctuation (RDF). As for FinFET, although the impact of fin-LER is more crucial to the threshold-voltage variation, the relative importance of gate-LER increases as the switching time variation is considered. Our presentation went smoothly and attracted several questions. Besides, we had one poster presentation addressing the impact of asymmetric halo implant on the mismatching properties of nanoscale MOSFETs.
二、與會心得
From the presentations in the VLSI Symposium and Silicon Nanoelectronics Workshop, we can see several trends for the VLSI field. First, the 3D system integration technology is becoming increasingly important for future technology generations. This is because 3D integration may provide capabilities to integrate heterogeneous technologies as well as to improve the system power efficiency, as demonstrated by the Intel’s high-performance floating point system prototype with 3D integrated SRAM. Besides the 3D integration, we can see the challenges facing CMOS lie mainly in Performance, Power, and Variability. To overcome these challenges, new materials (e.g., high-K dielectrics and Ge channel) and new device structures (e.g., FinFET and nanowire) are gaining more and more research efforts from both the industry and academia. Indeed, our 3 papers for the VLSI Symposium and Silicon
Nanoelectronics Workshop this year have mainly addressed the problems related to Variability. We appreciate the support from National Science Council that makes our dissemination of research results in Kyoto possible, and we will keep working diligently in this important area.
6A-2
Impact of Uniaxial Strain on Channel Backscattering Characteristics and Drain Current Variation for Nanoscale PMOSFETs
Wei Lee, Jack J.-Y. Kuo, Willian P.-N. Chen, Pin Su, Min-Chie Jeng*
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
*Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan
Abstract—Using an improved temperature-dependent method, this paper clarifies that channel backscattering of nanoscale PMOSFETs can be reduced by the uniaxially compressive strain. For the first time, the electrostatic potential of the source-channel junction barrier has been experimentally characterized with strain and gate voltage dependence. We further demonstrate that the strain technology can improve the drain current variation as well as the mismatching properties through the enhanced ballistic efficiency. Moreover, the improvement shows gate length and drain voltage dependence.
I. INTRODUCTION
Channel strain engineering has been actively pursued to enable the mobility scaling of CMOS devices. As the gate
length (Lg) scales into the nanoscale regime in which the carrier
ballistic transport prevails [1-2], strain-induced enhancement becomes more complicated [3-4]. Characterizing nanoscale strained MOSFETs from the perspective of channel
backscattering (rsat) becomes crucial to strain engineering [4-6].
However, it has been reported that uniaxially compressive
strain tends to increase the rsat of PMOSFETs [5-6]. The reason
is not clear and needs to be clarified. In addition, the impact of uniaxial strain on the drain current variation has rarely been known and merits investigation.
In this work, we examine the impact of uniaxial strain on backscattering characteristics in nanoscale PFETs and
demonstrate that rsat can be reduced by the uniaxially
compressive strain. Besides, impacts of strain on the electrostatic potential of the source-channel junction barrier (Fig. 1) and the non-threshold-voltage drain current variation (Fig. 2) are experimentally investigated for the first time.
II. CHANNEL BACKSCATTERING CHARACTERISTICS
The strained devices were fabricated by state-of-the-art process-induced uniaxial strained-silicon technology featuring SiGe source/drain and compressive contact etch stop layer (CESL) (Fig. 1) [5-8]. Fig. 3 shows that the saturated drain
current (Id,sat) and the linear drain current (Id,lin) of the strained
device are improved by 2.1X and 2.9X as compared with its unstrained counterpart, respectively.
According to the channel backscattering theory [2-3], rsat
depends on the mean-free path Ȝ and the critical length l as rsat
= 1/(1+Ȝ/l) [3]. To obtain rsat, we extracted Ȝ/l using the
self-consistent method [9], in which Ȝ/l and (ȕȝ-ȕl) can be
self-consistently determined by (1) & (2):
2 ) /( ) ( / ) ( ) 1 ( 2 , , , , w w w w T V V T V I T
Idsat dsat Tsat gs Tsat
l J J E E O P " (1), E E J E P X P O v ¸¸ ¹ · ¨¨ © § v l l T T k q q T k B therm B 0 1 2 " (2),
where ȕȝ, ȕl and Ȗ are defined as the temperature sensitivity of
the low-field mobility ȝ0, the critical length l and the thermal
velocity ȣtherm, respectively [10,11]. Contrary to the pervious
studies in [5,6,10,11], this self-consistent method [9] does not
assume constant ȕȝ and ȕl in the determination of Ȝ/l and rsat
(e.g., ȕȝ = -1.5 and ȕl = 1 in (1)). Fig. 4 shows significant
discrepancy in the extracted Ȝ/l between the self-consistent
(ȕȝ-ȕl) and (ȕȝ-ȕl) = -2.5. Note that the temperature dependence
of Ȝ/l can satisfy the constraint of Eq. (2) for the self-consistent
(ȕȝ-ȕl), but not for (ȕȝ-ȕl) = -2.5. Fig. 5 shows that the
self-consistently extracted (ȕȝ-ȕl) and rsat are strongly
dependent on Vgs. Note that the self-consistently extracted
(ȕȝ-ȕl) (Fig. 5(a)) presents more phonon-limited behavior (i.e.,
more temperature- sensitive) for the strained device, similar to
the measured Id,sat in Fig. 3(a). However, the assumption of
(ȕȝ-ȕl) = -2.5 results in insensitive rsat–Vgs dependence and
The reduced rsat in the compressive-strained PFET (rsat for
self-consistent (ȕȝ-ȕl) in Fig. 5(b)) can be referred to the
enhanced Ȝ (Fig. 6(b)), which can be extracted from [3]
) ) 1 ( ) 1 ( )( ( ) ) ( )( 2 )( ( sat sat T,sat gs g B T,lin gs d,sat ds d,lin r r V V L Ȝ Ȝ T k q V V I V I (3). Besides, we have confirmed that the enhancement of effective
mobility ȝ and ȣtherm (Figs. 6(c) and 6(a)) follows the relation of
Ȝ v (2kBTȝ0/qȣtherm) [10], i.e., 1.9X (Ȝ enhancement) ~ 3.3X (ȝ
enhancement) / 1.5X (ȣtherm enhancement). The strain effect on
the enhancement of 1/m* and the relaxation time IJ can also be
obtained: ~2.3X from (ȣtherm enhancement)2 and ~1.3X from (Ȝ
enhancement)/(ȣtherm enhancement), respectively. In addition,
we further extracted the critical length l by rsat = 1/(1+Ȝ/l). Fig.
7(a) shows the potential -kBT/q vs. (lT-l233K) characteristics,
which can be viewed as the potential gradient of the source-channel junction barrier (Fig. 1). It is clear that more backscattering events for the unstrained device with smaller Ȝ raise the electrostatic potential to higher energy to maintain the
same carrier density, as predicted in [12]. Moreover, the Vgs
dependence of the potential gradient in Fig. 7(b) explains the
Vgs dependence of rsat for the self-consistent (ȕȝ-ȕl) in Fig. 5(b).
III. DRAIN CURRENT VARIATION & BALLISTIC EFFICIENCY
A simple expression relating Id of nanoscale MOSFETs to
P0 has been derived by Lundstrom [3] as
B
I
Id d GP0 P0 1
G (4),
in which the sensitivity of Id to P0 is determined by the ballistic
efficiency B. Eq. (4) reveals that the impact of the P0 variation,
ı(P0)/P0, on the Id,sat variation, ı(Id,sat)/Id,sat, can be suppressed
when the ballistic efficiency B is enhanced. To ensure that the
VT variation does not affect the following analysis, we have
confirmed in Fig. 8 that the standard deviation of VT, ı(VT), as
well as the VT variation, ı(VT)/VT, are similar between strained
and unstrained devices. The linear dependence of ı(Id,sat)/Id,sat
on ı(P0)/P0 presented in Fig. 9 follows the prediction of Eq. (4),
in which the slope represents the degree of ballistic efficiency
B. The reduced slope for strained PFETs (Fig. 9) can be
explained by the Bsat enhancement (Bsat,strained-Bsat,unstrained) (Fig.
10). It is worth noting that the suppression of ı(Id,sat)/Id,sat, the
Bsat enhancement and the P enhancement are more significant
with decreasing Lg. Besides, we found that the B enhancement
decreases with decreasing Vds (Fig. 11), which may be referred
to the relation of B ~ Ȝ/(L+Ȝ) for low Vds, i.e., the Ȝ
enhancement is not important for Ȝ/(L+Ȝ) as L >> Ȝ. Such Vds
dependence of the B enhancement results in the weak
suppression in the ı(Id)/Id vs. ı(P0)/P0 characteristics measured
at Vds = 0.3 V (Fig. 12).
Statistics on the mismatch in drain current (ǻId) and
threshold voltage (ǻVT) were analyzed for identical devices in a
matching pair configuration on 60 dies (Fig. 13). Fig. 14 shows that the drain current mismatch in the high gate bias regime is
dominated by the non-VT mismatch. Moreover, improved
matching performance for strained PFETs can be observed in Fig. 14 and Fig. 15. It is worth noting that the reduction of
ı(ǻId/Id) for strained PFETs (Fig. 15) is more significant for
|Vds| = 1 V than for |Vds| = 0.05 V. This result can be understood
from the Vds dependence of the B enhancement (Fig. 11).
IV. CONCLUSION
Using an improved temperature-dependent method, we
have shown that the rsat of nanoscale PMOSFETs can be
reduced by the uniaxially compressive strain. For the first time, the electrostatic potential of the source-channel junction barrier
has been experimentally characterized with strain and Vgs
can improve the drain current variation as well as the mismatching properties through the enhanced ballistic
efficiency. Moreover, the improvement shows Lg and Vds
dependence.
ACKNOWLEDGEMENTS: This work was supported in part by the National Science Council of Taiwan under Contract NSC 97-2221-E-009-162, and in part by the Ministry of Education in Taiwan under ATU Program.
REFERENCE: [1] K. Natori, JAP, 76, 4879, 1994 [2] M. S. Lundstrom, EDL, 18, 361, 1997 [3] M. S. Lundstrom, EDL, 22, 293, 2001 [4] T. Skotnicki et al., TED, 55, 96, 2008 [5] H.-N. Lin et al., EDL, 26, 676, 2005 [6] H.-N. Lin et al., IEDM, 141, 2005 [7] J. Kuo et al., TED, 2009 [8] P.-N. Chen et al.,TNANO, 7, 538, 2008 [9] W. Lee et al., submitted to 2009 VLSI Symp. [10] M.-J. Chen et al., IEDM, 39, 2002 [11] M.-J. Chen et al., TED, 51, 1409, 2004 [12] A. Svizhenko et al., TED, 50, 1459, 2003
|Vgs-VT|=0.8V |Vds|=0.05V Bsa t,s tr ai ne d -Bsa t,u ns tr ai ne d 0,sȝ tra in ed-ȝ 0,unstr ained (a .u .) |Vgs-VT|=0.8V |Vds|=1.3V 0.07 0.08 0.09 0.1 0.11 0.2 0.5 0.8 1.1 1.4 |Vds| (V) B st ra in ed -B un str ai ne d PMOSFETsLg=60nm |Vgs-VT|=0.8V
Fig. 13. Schematics of the pair transistors for mismatching
measurements of ǻI and ǻV.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100 data_Controlled data_Strained Vt mismatch_Controlled Vt mismatch_Strained Others_Controlled Others_Strained V 2 ( ' I d,lin /I d,lin ) (% ) |VGS-VT,sat| (V) PFET Lg=54nm W=0.3Pm unStrained data Strained data VT mismatch unS. VT mismatch S.
Non-VT mismatch unS.
Non-VT mismatch S. |VGS-VT| (V)
"
Source Drain (1-rsat) rsat 1 Qinv,Ӽinj"
Source Drain (1-rsat) rsat 1 Qinv,Ӽinj S D G Stress-engineered:STI, SiGe, CESL ȝ0fluctuation
S D
G Stress-engineered:
STI, SiGe, CESL ȝ0fluctuation
1 2 3 4 5 6 0.2 0.5 0.8 |Vgs-VT,lin| (V) Ȝ (nm ) Strained unStrained (b)Vds=-20~20mV ~1.9X 1 2 3 4 5 6 0.2 0.5 0.8 |Vgs-VT,lin| (V) no rm al ized ef fec tiv e m obi lity (c) |Vds|=0.05V unStrained Strained ~3.3X 1 2 3 0.4 0.7 1 |Vgs-VT,sat| (V) nor m al iz ed ther m al ve loci ty Strained unStrained (a) |Vds|=1.3V ~1.5X 0 1 2 3 4 0 1 2 3 4 ı(ȝ0)/ȝ0 (%) ı( I d, sa t )/I d, sa t (% ) unStrained Strained PMOSFETs |Vgs-VT| = 0.8V |Vds| = 1.3V Lg= 75~50nm Suppression Long channel Short channel
Fig. 3. Measured Id vs. Vgs characteristics for
50-nm-Lg PMOSFETs with and without
uniaxially compressive strain at T = 233~373 K
for (a) |Vds| = 0.05 V and (b) |Vds| = 1.3 V.
S D
G
S D
G A schematic of pair transistors in one die
60 dies within 300 mm wafer are measured. VT1, Id1 VT2, Id2 W Lg 0.9 1 1.1 0.9 1 1.1 VT/VT_mean I ds at /I ds at _m ea n Idsat measured@|Vgs|=1.3V Idsat extracted@|Vgs-Vt|=0.8V N on -V T v ari ati on PFETs Lg=500~50nm VDS=1.3V
Fig. 12. ı(Id)/Id vs. ı(ȝ0)/ȝ0 characteristics
for strained and unstrained PFETs with L
Fig. 9. ı(Id,sat)/Id,sat vs. ı(ȝ0)/ȝ0
characteristics for strained and unstrained
PFETs with Lg = 50 ~ 500 nm at Vds= 1.3 V.
Fig. 8. Comparison of ı(VT) and
ı(VT)/VT for strained and unstrained
PFETs.
Fig. 1. The impact of uniaxially
compressive strain on
backscattering coefficients rsat and
Id fluctuation is investigated.
Fig. 4. Extracted Ȝ/l vs. T
characteristics showing the need of
self-consistent (ȕȝ-ȕl).
Fig. 5. Extracted (a) (Eȝ-El) and (b) rsat vs. Vgs
characteristics for PFETs with and without
uniaxially compressive strain. Rsd was corrected.
Fig. 6. Extracted (a) thermal velocity ȣtherm, (b)
mean-free path Ȝ and (c) effective mobility ȝ vs. Vgs
characteristics for strained and unstrained PFETs.
Fig. 7. Extracted potential –kBT/q vs. (lT-l233K)
characteristics shows (a) the strain dependence
and (b) the Vgs dependence.
Fig. 10. Bsat enhancement and ȝ
enhancement vs. Lg characteristics
for strained and unstrained PFETs .
Fig. 14. Comparison of the measured
ı2(ǻI/I) with the mismatch model. Fig. 15. Pelgrom plot of the standarddeviation of normalized ǻI,
* 2 mT kB therm S X v * 2 mkBT W Ov PvmqW* O O O O o m B l Lg 2 0 1 2 3 4 5 6 7 8 9 10 0.3 0.6 0.9 1.2 |Vgs| (V) I d, sa t (1 0 4 A /ȝ m ) 233K 298K 373K Strained unStrained ~2.1X (a) |Vds|=1.3V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.3 0.6 0.9 1.2 |Vgs| (V) I d,l in (1 04 A /ȝ m ) 233K 298K 373K unStrained Strained ~2.9X (b) |Vds|=0.05V -2.1 -1.7 -1.3 -0.9 0.3 0.6 0.9 |Vgs-VT,sat| (V) (E ȝ -E l ) Strained unStrained (a) Lg=50nm |Vds|=1.3V Rsd~125/214 (ohm/ȝm) for Strained/unStrained 0.2 0.4 0.6 0.8 1 0.3 0.6 0.9 |Vgs-VT,sat| (V) r sa t self-consistent (Eȝ-El) (b) unS. S. Rsd corr. No Yes (Eȝ-El) = -2.5 0 0.5 1 1.5 lT-l233K (nm) 0.4V 0.5V 0.6V 0.7V 0.8V Strained PFET Lg=50nm |Vgs-VT,sat| (b) -35 -30 -25 -20 -15 0 0.2 0.4 0.6 lT-l233K (nm) -kB T/ q (m V) Strained unStrained l @ |Vgs-VT,sat|=0.8V backscattering source to drain flux (a)
Fig. 11. Vds dependence of the
ballistic-efficiency enhancement.
B is near Ȝ/(2l+Ȝ) for high Vdsand
Ȝ/(Lg+Ȝ) for low Vds. 0 1 2 3 4 0 1 2 3 4 ı(ȝ0)/ȝ0 (%) ı( I d )/I d (% ) unStrained Strained PMOSFETs |Vgs-VT| = 0.8V |Vds| = 0.3V
Fig. 2. Normalized Id,sat vs.
normalized VT characteristics
showing the impact of the non-VT
Investigation of Switching Time Variations for FinFET and Bulk MOSFETs
Using the Effective Drive Current Approach
Yu-Sheng Wu, Ming-Long Fan, and Pin Su
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan Tel:+886-3-5712121, Fax:+886-3-5724361, E-mail: [email protected]
Introduction
With MOSFET scaling, the impact of random dopant fluctuation (RDF) and line edge roughness (LER) on the threshold voltage (Vth) variation for MOSFETs is growing and
being extensively examined [1-4]. For logic circuits, the variation of signal switching time due to RDF and LER is especially important. Whether there is any gap between Vth and
switching time variations merits investigation. In this work, we investigate the switching time variation for FinFET and bulk MOSFETs using the approach of effective drive current in CMOS inverters [5].
Methodology
We decouple the switching time (ST) variation into transition charge (∆Q) variation and effective drive current (Ieff)
variation. The ST can be defined as ∆Q / Ieff [6], where ∆Q is the
transition charge between logic “ON” and “OFF” states. The ∆Q for an NFET can be calculated by Qn (VGS = VDD, VDS = 0.05 V)
－ Qn (VGS = 0V, VDS = VDD). The Ieff for an NFET can be
approximated as [IDS (VGS = VDD, VDS = 0.5VDD) + IDS (VGS =
0.5VDD, VDS = VDD)] / 2 [5]. Therefore, in contrast to the
time-consuming mixed-mode transient simulation, only DC simulation for a single device is needed to derive ∆Q and Ieff.
More importantly, the effective current approach may provide physical insights in the assessment of the switching time variations.
To assess the RDF in bulk MOSFETs, we have carried out the atomistic device simulation using the Monte Carlo approach [2]. To avoid the charge trapping in the sharp Coulomb potential well and hence the mesh size dependences of the simulation results, we have employed the density gradient method in our atomistic simulation [7]. Fig. 1(a) shows a sample used in our RDF atomistic simulation for bulk devices. To assess the LER, the line edge patterns were derived using the Fourier synthesis approach [3], and then the Monte Carlo simulation was performed. Fig. 1(b) shows a sample used in the LER simulations for bulk devices. The multi-gate structure we study in this work is the lightly doped FinFET with aspect ratio = 2 [Fig. 2(a)]. The gate-LER and fin-LER are considered as independent variation sources for FinFET [4]. Fig. 2(b) and (c) show samples used in our Monte Carlo simulations for gate- and fin-LER for FinFET, respectively.
Results and Discussion Bulk MOSFET
Fig. 3(a) compares the impacts of RDF and LER on the saturation threshold voltage (Vth,sat) variations of bulk
MOSFETs. It can be seen that the standard deviation of Vth,sat
(σVth,sat) due to RDF is larger than that due to LER.
Nevertheless, Fig. 3(b) shows that the standard deviation of ST (σST) due to LER is larger than that due to RDF. Since ST = ∆Q / Ieff, the normalized standard deviation of ST (σST / µST) can
be approximated as |σST / µST| ≈ |σ∆Q / µ∆Q - σIeff / µIeff|,
where µST, µ∆Q and µIeff are the mean values of ST, ∆Q and Ieff,
respectively. Fig. 4 shows the |σST / µST|, |σ∆Q / µ∆Q|, and |σIeff / µIeff| (normalized standard deviation of ST, ∆Q and Ieff,
respectively) caused by RDF and LER. It can be seen that the |σST / µST| due to RDF is roughly equal to the difference of |σIeff / µIeff| and |σ∆Q / µ∆Q| due to RDF. However, the |σST /
µST| due to LER is roughly equal to the sum of |σIeff / µIeff| and
|σ∆Q / µ∆Q| due to LER. The results in Fig. 4 can be explained as follows. The impact of RDF on MOSFETs stems from the variation of the effective channel doping (Nch,eff). For devices
|σST / µST| is roughly equal to the difference of |σ∆Q / µ∆Q| and |σIeff / µIeff| because the quantities of σ∆Q and σIeff have the
same sign. In other words, the impacts of RDF on ∆Q and Ieff
are mutually canceled and |σST / µST| is reduced.
The impact of LER on bulk MOSFETs results from the variation of the effective channel length (Leff). For devices with
shorter Leff, the Vth is smaller because of the short channel effect
and hence the Ieff is larger. As for ∆Q, devices with shorter Leff
possess smaller ∆Q because ∆Q is proportional to the gate area (W × Leff). Thus, Ieff and ∆Q are negatively correlated [Fig.
5(b)]. Therefore, |σST / µST| is roughly equal to the sum of |σ∆Q / µ∆Q| and |σIeff / µIeff| because the quantities of σ∆Q and
σIeff have the opposite sign. In other words, the |σST / µST| is
larger than either |σ∆Q / µ∆Q| or |σIeff / µIeff|. Fig. 6 indicates
that the relative importance of LER for switching time variation is larger as compared with that for Vth variation.
FinFET
Fig. 7(a) compares the impacts of gate-LER and fin-LER on Vth,sat variations of FinFET. It can be seen that σVth,sat due to
fin-LER is larger than that due to gate-LER. Nevertheless, Fig. 7(b) shows that σST due to gate-LER is larger than that due to fin-LER. Fig. 8 shows the |σST / µST|, |σ∆Q / µ∆Q|, and |σIeff /
µIeff| caused by gate-LER and fin-LER. The |σST / µST| due to
gate-LER is roughly equal to the sum of |σIeff / µIeff| and |σ∆Q /
µ∆Q|. This is because Ieff and ∆Q due to gate-LER are
negatively correlated [Fig. 9(a)]. However, the |σST / µST| due to fin-LER is roughly equal to the difference of |σIeff / µIeff| and
|σ∆Q / µ∆Q|. The impact of fin-LER on FinFET stems from the variation of the effective fin width (Wfin). For lightly devices
with smaller Wfin, the Vth is larger because of the suppression of
short channel effect [1] and hence the Ieff is smaller. As for ∆Q,
devices with smaller Wfin possess smaller ∆Q because ∆Q is
proportional to the gate area. Thus, the Ieff and ∆Q are positively
correlated [Fig. 9(b)]. The impacts of fin-LER on ∆Q and Ieff are
mutually canceled and |σST / µST| is reduced. Fig. 10 indicates that the relative importance of gate-LER for switching time variation is larger as compared with that for Vth variation.
Conclusions
We have investigated the impact of LER and RDF on switching time variations of bulk MOSFETs and FinFET using the effective drive current approach. The ST variation can be decoupled into ∆Q variation and Ieff variation. Our results
indicate that for bulk MOSFETs, the ST variation caused by LER may be larger than that caused by RDF. Although RDF has been recognized as the main variation source to Vth variation,
LER becomes more crucial to the ST variation of bulk MOSFETs. As for FinFET, although the impact of fin-LER is more crucial to Vth variation, the relative importance of
gate-LER increases as the ST variation is considered. Our study may provide insights for device and circuit designs using advanced CMOS technologies.
Acknowledgement
This work was supported in part by the National Science Council of Taiwan under contract NSC 97-2221-E-009-162 and in part by the Ministry of Education in Taiwan under ATU Program.
References
[1] Y. S. Wu et al., IEEE TNANO, vol. 7, No. 3, p.299, 2008. [2] D. Frank et al., VLSI Sym., p.169, 1999.
[3] A. Asenov et al., IEEE TED, vol. 50, No. 5, p.1254, 2003. [4] E. Baravelli et al., IEEE TED, vol. 54, No. 9, p.2466, 2007.
Fig. 2. (a) The nominal FinFET structure with aspect ratio = 2. (b) One of the samples with gate-LER. (c) One of the samples with fin-LER. Fig. 1. The simulated bulk devices in this study. (a) One of
the samples with RDF and (b) one of the samples with LER.
Fig. 3. (a) Comparison of the standard deviations of Vth,sat due to RDF and LER in bulk MOSFETs. (b) Comparison of the standard deviations of ST due to RDF and LER in bulk MOSFETs.
Fig. 5(a). The correlation of Ieff distribution and ∆Q distribution for bulk MOSFETs with RDF.
Fig. 5(b). The correlation of Ieff distribution and ∆Q distribution for bulk MOSFETs with LER.
Fig. 6. The relative importance of Vth,sat and ST variation caused by LER for bulk MOSFETs. Assume that RDF and LER are independent.
Fig. 7. (a) Comparison of the standard deviations of Vth,sat due to gate- and fin-LER in FinFET. (b) Comparison of the standard deviations of ST due to gate- and fin-LER in FinFET.
Fig. 8 The normalized standard deviations of ST, Ieff and ∆Q due to gate- and fin-LER in FinFET.
Fig. 9 The correlations of Ieff distribution and ∆Q distribution for FinFET with (a) gate-LER and (b) fin-LER.
(a) (a) (b) (c) (b) (a) (b) 0 20 40 60 80 σ 2 LE R / ( σ 2 RDF + σ 2 LER ) [%] ST Vth,sat 0 20 40 60 80 σ 2 Ga te -L E R / ( σ 2 Gate-LE R + σ 2 Fin-LE R ) [ % ] ST Vth,sat
Fig. 4. The normalized standard deviations of ST, Ieff and ∆Q due to RDF and LER in bulk MOSFETs.
(a) (b)
(a) (b)
Fig. 10 The relative importance of Vth,sat and ST variation caused by 108.82 134 LER 140.75 134 RDF source 108.82 134 LER 140.75 134 RDF source Vth( )mV σVth( )mV 0 40 80 120 160 200 σ Vth,s at [mV] LER RDF 0.221 1.490 LER 0.145 1.645 RDF source 0.221 1.490 LER 0.145 1.645 RDF source ST( )psσST( )ps 0.0 0.1 0.2 0.3 LER σ ST [p s] RDF 26.9 270 Fin-LER 21.5 277 Gate-LER source 26.9 270 Fin-LER 21.5 277 Gate-LER source Vth( )mV σVth( )mV 0 10 20 30 40 σ Vth ,sa t [mV] Fin-LER Gate-LER 0.122 1.975 Fin-LER 0.137 1.916 Gate-LER source 0.122 1.975 Fin-LER 0.137 1.916 Gate-LER source ST( )ps σST( )ps 0.00 0.05 0.10 0.15 0.20 σ ST [ps] Fin-LER Gate-LER 5.5x10-17 6.0x10-17 6.5x10-17 7.0x10-17 3.0x10-5 3.2x10-5 3.4x10-5 3.6x10-5 3.8x10-5 Gate-LER Ieff [A] ∆Q [C] 6.0x10 -17 7.0x10-17 8.0x10-17 9.0x10-17 3.0x10-5 4.0x10-5 5.0x10-5 Ieff [A ] ∆Q [C] Fin-LER 1.8x10-17 1.9x10-17 2.0x10-17 8.0x10-6 1.0x10-5 1.2x10-5 1.4x10-5 1.6x10-5 Ieff [A] ∆Q [C] RDF 1.6x10-17 1.8x10-17 2.0x10-17 2.2x10-17 8.0x10-6 1.0x10-5 1.2x10-5 1.4x10-5 1.6x10-5 1.8x10-5 LER Ieff [A] ∆Q [C] 0 5 10 15 20 µIeffµ∆Q µST σIeffσ∆Q LER N orma lied St and ard Devia tion [ % ] RDF σST µIeffµ∆Q µST σIeffσ∆Q σST 0 2 4 6 8 10 12 Fin-LER No rm alie d S tand ard De viation [%] Gate-LER µIeffµ∆Q µST σIeffσ∆Q σST µIeffµ∆Q µST σIeffσ∆Q σST
