R A P I D C O M M U N I C AT I O N
Nano-crystallized titanium oxide resistive memory with uniform
switching and long endurance
C.H. Cheng· Albert Chin
Received: 25 November 2012 / Accepted: 3 January 2013 / Published online: 15 January 2013 © Springer-Verlag Berlin Heidelberg 2013
Abstract We report a novel resistive random access mem-ory using tri-layer dielectrics of GeOx/nano-crystal TiO2/
TaON and low cost top Ni and bottom TaN electrodes. Ex-cellent device performance of ultra-low 720 fJ switching en-ergy, tight distributions of set/reset currents, and exception-ally long endurance of 5× 109cycles were achieved simul-taneously. Such excellent endurance may create new appli-cations such as those used for Data Centers that are ascribed to the higher-κ nano-crystal TiO2, hopping pass via grain
boundaries, and fast switching speed of 100 ns to improve the dielectric fatigue during endurance stress.
1 Introduction
According to International Technology Roadmap for Semi-conductors (ITRS) [1], the Flash non-volatile memory (NVM) continues to scale down into sub-20 nm, by replac-ing the current poly-Si floatreplac-ing-gate (FG) with SiN charge-trapping (CT) structure [2–4]. However, the degraded en-durance from 105 to 104 program/erase cycles is the fun-damental physics limitation due to the smaller number of charges stored in the sub-20 nm cell size. Such degraded endurance is unsuitable for high-end products; therefore, new NVM devices should be developed. To address this
C.H. Cheng (
)Department of Mechatronic Technology, National Taiwan Normal University, Taipei 106, Taiwan
e-mail:[email protected] Fax: +886-2-23583074 A. Chin
Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
concern, non-charge-based resistive random access mem-ory (RRAM) has attracted considerable attention [5–13]. However, the high set/reset currents, high forming power, poor endurance, and required extra large-size transistor for current compliance are the difficult challenges for RRAM. However, the set/reset cycle times of 106must still be
im-proved to realize the ideal green NVM with low switch-ing energy, long endurance, and high switchswitch-ing speed. In this letter, we report a novel high endurance and ultra-low switching power RRAM device, where only 4 µW setting power, ultra-low reset power of 200 nW, large resistance window >50X, favorable switching uniformity, and excel-lent cycling endurance (up to 5× 109cycles) were achieved simultaneously. Such high performances were reached in designing the Ni/GeOx/nano-crystal (nc) TiO2/TaON/TaN
RRAM device, where the excellent endurance is 4 to 5 or-ders of magnitude larger than the highest quality Flash mem-ory [1–4]. The excellent endurance is related to hopping conduction via grain boundaries of nc-TiO2, fast switching
speed of 100 ns, and the using high-κ dielectrics to lessen the dielectric fatigue during stress. The exceptionally long endurance and low switching energy RRAM not only sat-isfy the portable Solid-State Drive (SSD) in computers, but may also create new applications such as those used for Data Center, to replace the high power consumption of hard discs.
2 Experiments
The RRAM devices were integrated into a VLSI backend for an embedded memory application. First, a 200-nm-thick backend SiO2was formed on the Si substrates. Then 100 nm
TaN was deposited by sputtering. After patterning the bot-tom TaN electrode, the 24-nm-thick TaON film was de-posited by sputtering and followed by oxygen annealing at
400 ◦C for 10 min. Subsequently, the 26-nm-thick TiO2
film was deposited by sputtering in a gas mixture with 5 % O2 in Ar ambient on the TaON/TaN. Then the TiO2 film
was annealed at 400 ◦C for 5 min to form crystallized TiO2, where the crystallinity of TiO2[14] was measured by
transmission electron microscopy (TEM) and a fast Fourier transition (FFT) technique. The amorphous TiO2 (a-TiO2)
control sample was also fabricated for performance com-parison. Following that, a 6-nm-thick GeOx was deposited to form the tri-layer dielectrics of the GeOx/TiO2/TaON.
Finally, a 50-nm-thick Ni was deposited and patterned to form the top electrode by a metal mask with an area of 11300 µm2. The fabricated devices were characterized by capacitance-voltage (C-V ), current-voltage (I -V ), switch-ing speed, and endurance measurements usswitch-ing an Agilent 4284 LCR meter, 4156 semiconductor parameter analyzer, and 81110 pulse generator, respectively. The bottom TaN of RRAM was grounded for related electrical measurement.
3 Results and discussion
Figure1(a) shows the swept I -V curves of the Ni/GeOx /nc-TiO2/TaON/TaN RRAM. Favorable resistive switching
char-acteristics were measured, where a large resistance window >100 at 0.5 V was obtained. In addition to the forming-free and self-compliance switching, this RRAM can be set to a low resistance state (LRS) at a low power of 4 µW (1 µA at 4 V) and reset to a high resistance state (HRS) at an extremely low power of 200 nW (−40 nA at −5 V). The low LRS current is attributed to the large internal resis-tance by hopping conduction [15], which also results in the measured forming-free and self-compliance operation. The RRAM with asymmetric I -V and exceptionally small re-set current are similar to the asymmetric I -V and very low revise leakage current in a Schottky diode. The asymmet-ric switching I -V curves are ascribed to the different work functions of the bottom TaN (4.6 eV) and top Ni electrodes (5.1 eV) [16]. The top GeOx layer is vital in forming the resistive switching behavior, as the control devices without GeOx have no resistance hysteresis loops (not shown). To explore such low switching currents, the current conduction mechanism was analyzed. Figure1(b) shows the measured and simulated I -V characteristics at HRS and LRS, respec-tively. The small HRS current is due to the Frenkel–Poole emission via the top Ni. The current at LRS is governed by a space-charge-limited current (SCLC) via dielectric defects, for electrons injected from the bottom TaN. Such resistive switching with negative TC has been previously attributed to the hopping conduction via charged oxygen and nitrogen va-cancies [12,13], and is further verified by the hysteresis loop found in C-V measurements shown in Fig. 1(c). Here the voltage change for set and reset operation is 5 V and−6 V,
Fig. 1 (a) Swept I -V curve, (b) I -V at HRS and LRS by fitting with
Frenkel–Poole and SCLC conduction mechanisms, respectively, and (c) 100 kHz C-V curves of Ni/GeOx/nc-TiO2/TaON/TaN RRAM
de-vices. The inset figures are the schematic energy band diagram with charged oxygen vacancies under set and reset conditions
respectively. It is important to notice that the C-V hysteresis loop represents the change of charges by Q= C × V . However, the C-V hysteresis curve in this RRAM device is quite different from the C-V hysteresis loop found in Flash
memory [2–4]. This is due to the different MIM and MIS structure used for RRAM and Flash, respectively. During the set with a positive voltage, the charged oxygen vacan-cies can be formed by injected electrons from the bottom TaN electrode, resulting in a higher capacitance, shown in the inserts of Fig.1(c). During the reset, the injected elec-trons from the top Ni electrode can disrupt the weakly linked hopping conduction pass by annihilating the charged vacan-cies at ultra-low energy:
VGe–O2+ x + 2e
−+ Ge–O
x→ Ge–O∗x. (1)
Here, the VGe–O2+
xis the oxygen vacancy in GeOxfor the hop-ping conduction. The change of vacancies charges, shown in the area of C-V hysteresis loop, in turn decreases the capac-itance density at HRS state.
The nc-TiO2 performs a vital function in attaining low
switching power in RRAM. Figures 2(a), 2(b), and 2(c) show the switching I -V curves, 60-ms pulsed switch-ing stress, and cross-sectional TEM of the Ni/GeOx /a-TiO2/TaON/TaN RRAM devices, respectively, where
differ-ent nc-TiO2(anatase phase) or a-TiO2in the RRAM devices
were used for comparison. As shown in Fig.2(c), the anatase TiO2with native shallow-level defects may contribute
supe-rior electron transport for fast resistive switching. Although similar I -V switching behavior can be observed, the con-trol device with a-TiO2 requires larger set and reset
volt-ages of 6 V and −8 V, respectively. Furthermore, signifi-cantly higher switching currents for the set (18 µA) and reset (1.2 µA) were found in the RRAM device with a-TiO2layer,
as opposed to those with nc-TiO2. To investigate further
such large differences in nc-TiO2 and a-TiO2 RRAM, the
devices were under 60 ms set and 60 ms reset stress. Highly stable switching cycles were discovered in the RRAM de-vice with an nc-TiO2layer. By sharp contrast, the control
de-vice with a-TiO2yields a small initial HRS/LRS ratio <10X
at a read voltage of 1 V, where the HRS/LRS memory win-dow shrinks with increasing set/reset cycles. The decreased LRS current after continuous set/reset cycling stress may be related to the redistribution of charged oxygen and nitrogen vacancies [13] under a continuous switching electric field. From the cross-sectional TEM images of the Ni/GeOx /nc-TiO2/TaON/TaN RRAM, a small size of 3–9 nm nc-TiO2
can be clearly observed in the enlarged TEM picture. The nc-TiO2was confirmed by FFT patterns that further forms
the higher dielectric constant (κ) anatase phase structure from X-Ray Diffraction (XRD) measurements. Therefore, the lower switching power and more favorable long-pulsed switching endurance should be related to the existing grain boundaries in nc-TiO2. Research has shown that the grain
boundaries exhibit an exceptionally high density of dangling bands; this in turn allows the hopping conduction pass to form via grain boundaries at a lower set power. By contrast,
Fig. 2 (a) Swept I -V curves, (b) resistive switching behaviors under
60 ms set/reset stress cycles and (c) cross-sectional TEM images of Ni/GeOx/TiO2/TaON/TaN RRAM with nc-TiO2(anatase structure) or
control a-TiO2layer
a high set power is required to form defects for hopping conduction in the densified amorphous material.
The distribution of resistance states is a critical con-cern for RRAM. Figure 3(a) shows the measured cur-rent distributions of Ni/GeOx/nc-TiO2/TaON/TaN RRAM,
Fig. 3 (a) Current distributions and (b) MLC operation of Ni/GeOx/
nc-TiO2/TaON/TaN RRAM
where tight current distribution for both LRS and HRS was achieved. The excellent switching uniformity is linked to the low power operation with low set/reset currents and self-compliance set/reset operation, which is significantly more favorable than conventional RRAM using metallic fil-ament conduction. As seen in Fig.3(b), the RRAM is also capable for multi-level cell (MLC) storage. The MLC func-tion explains that HRS current dominated by Frenkel–Poole emission has various trap levels, which can be set and reset using appropriate bias conditions for mass storage applica-tions.
Endurance is a severe limiting factor for conventional metallic filament RRAM. Figure4(a) shows the measured endurance characteristics under an over-stressed 7.2 V set pulse and−6 V reset pulse at switching speed of 100 ns. The endurance to 5× 109cycles for fast 100 ns pulse was obtained, which is 4 to 6 orders of magnitude higher than the existing Flash memory at an ultra-low 720 fJ switching energy. Excellent uniformity≥109cycles are also obtained at 100 ns switching that is a strong merit of this device. Such excellent endurance is ascribed to the fast switching speed, low switching power, easy hopping via grain boundaries, and higher-κ nc-TiO2 (κ >40) to a lower stress electrical
field.
Fig. 4 (a) 100-ns-pulsed set/reset endurance characteristics and
(b) current distribution during cycling endurance test of Ni/GeOx/
nc-TiO2/TaON/TaN RRAM
Figure4(b) shows HRS/LRS currents distribution during long endurance cycling. The current distribution is not de-graded during the endurance cycles of <109cycles, except for slight variation on HRS/LRS distributions. However, the continued cycling stress results in degraded switching uni-formity and small resistance window at the end of 5× 109 cycles, indicating that increased conductive trap centers in RRAM deteriorate trap dependence of Frenkel–Poole HRS and SCLC LRS currents.
4 Conclusion
We demonstrate an ultra-low switching energy RRAM with self-compliance operation, large resistance window, favor-able switching uniformity, and excellent endurance cycles of 5× 109. The excellent endurance is attributed to the combined contribution of low switching energy, easy hop-ping via grain boundaries and a lower stress electric field in higher-κ anatase TiO2, lessening the dielectric fatigue under
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