[PDF] Top 20 Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
Has 10000 "Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process" found on our website. Below are the top 20 most common "Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process".
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
... nLDMOS in high-voltage technologies has been known to have poor ESD ...the ESD robustness of snapback-based ...waffle layout style and the ESD trigger ... See full document
9
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
... A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, ... See full document
21
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
... ESD protection schemes, the high-speed receiver interface circuit (Receiver_0) without ESD protection was also fabricated in the same ...the ESD-protected ... See full document
10
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... finger-type layout pattern and the corresponding cross-sectional view of the substrate-triggered stacked- NMOS device are shown in ...3(a) and (b), respectively. As shown in the ... See full document
9
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
... Abstract—Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated ...oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded ... See full document
8
Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
... proposed design com- bines P N-well diodes and P-well/N diodes to form the embedded P /N-well/P-well/N SCR paths by using layout skill, and this design also includes the trigger ... See full document
10
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
... new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm ...V CMOS process. The layout area of the new ... See full document
11
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... SCR design is pro- posed for effective on-chip RF ESD protection for 60-GHz fre- ...under ESD stress ...of ESD protec- tion device under normal RF circuit operating ... See full document
10
ESD protection design for CMOS RF integrated circuits using polysilicon diodes
... novel ESD protection design with stacked polysilicon diodes for RF ICs has been proposed and ...realized in general sub-quarter- micron CMOS ...with layout para- ... See full document
10
Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
... analog ESD protection circuit with a very low and almost constant input capacitance, high ESD level, but no series resistance, has been successfully designed and verified ... See full document
22
Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
... of ESD detection circuit under 0-to-6 V ESD-like transition on ESD bus line (the line for node e overlaps with the line for node ...VDD-Tolerant ESD Clamp Circuits The 3 × ... See full document
10
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... Manager in the VLSI Design Division of the Computer and Communica- tion Research Laboratories (CCL), Industrial Tech- nology Research Institute (ITRI), ...Professor in the Department of Elec- ... See full document
8
High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
... VLSI Design Division, Computer and Communication Re- search Laboratories, Industrial Technology Research Institute, ...Professor and Vice President of I-Shou University, Kaohsiung, ...University, ... See full document
6
High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection
... eral DMOS (nLDMOS) has been significantly increased in this letter through the waffle-layout style with body-current ...on high-voltage nLDMOS has been successfully verified in a ... See full document
3
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
... a voltage drop across the NW ...Vdd and gates were connected to another end of NW resistor,the voltage drop between two ends of the NW resistor also appeared equally across gates and sources ... See full document
7
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
... CDM ESD test, the device is initially charged at a negative voltage through the VSS and VSSIO ...1 and path 2 shown in Fig. 3. The high voltage between the grounded input ... See full document
4
On-chip ESD protection design by using polysilicon diodes in CMOS process
... Professor in the Department of Electrical Engineering, Portland State University, Portland, ...Engineering and Applied Science with the National Science ...papers in international journals and ... See full document
11
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
... as high as two to three times the supply voltage ...SCR ESD protection designs with a diode from output pad to limits the maximum signal swing at RF ...large-swing-tolerant ESD ... See full document
8
Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
... the ESD-generated heat across each diode, and the ESD robustness can be ...pair and high-speed circuits, and D P3 –D N3 pair are C 1 , C 2 , and C 3 , ...This ... See full document
7
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... VLSI Design Department, Computer and Communication Research Labo- ratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, ...R.O.C. In 1998, he was the Department Manager of the VLSI ... See full document
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