[PDF] Top 20 On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
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On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
... Abstract—CMOS technology has been widely used to produce many integrated ...However, the thinner gate oxide in nanoscale CMOS technology seriously increases ... See full document
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Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... overview on ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...improve ESD level of the mixed-voltage ... See full document
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Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
... IRCUIT The proposed ultra-low-leakage power-rail ESD clamp circuit is shown in ...3. The p-type substrate-triggered sil- icon-controlled rectifier (SCR) device is ... See full document
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Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
... Taiwan, in 1993. He has been the Department Manager of the VLSI Design Division, Computer and Communication Re- search Laboratories, Industrial Technology Research Institute, ... See full document
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Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
... Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology Chih-Ting Yeh, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE ... See full document
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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... shown in Fig. 14. The It2 of the input pad under PS-mode ESD stress with silicide blocking on pMOS and nMOS devices is 3 A, and that without silicide blocking is 2 ... See full document
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Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
... AIL ESD C LAMP C IRCUIT A. Circuit Schematic The new proposed power-rail ESD clamp circuits of the ultralow standby leakage are shown in ... See full document
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Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
... addition, the latch-on event in BFET2 or Modified3 would vanish by some modifications of layout style and n-well ...Consequently in layout, the width of N+/n-well minority ... See full document
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Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
... that the failure on the traditional power- rail ESD clamp circuit and design A is due to a high trigger current flowing through M p ...at the expense ... See full document
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Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
... Manager in the VLSI Design Division of Computer & Communication Research Laboratories (CCL), Industrial Tech- nology Research Institute ...Advisor in the Integrated ... See full document
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Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
... investigated in a 0.6-lm CMOS process. By using the substrate-triggered technique, the DTDB, STDB, and STLB devices can provide much higher ESD ro- bustness within a smaller layout ... See full document
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High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
... Manager with the VLSI Design Division, Computer and Communication Re- search Laboratories, Industrial Technology Research Institute, ...Professor with the Institute of ... See full document
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Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
... investigate the capacitance of different metal-layer capaci- tors, the test devices of MIM and MOM capacitors had been fabri- cated in the silicon chip with a 65 nm ... See full document
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New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
... been the Chair Professor and Vice President with I-Shou University, Kaohsiung, ...Professor with the Department of Electronics Engineering, Na- tional Chiao Tung University, and also ... See full document
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The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
... joined the VLSI Design Department of the Computer and Communication Research Labora- tories (CCL), Industrial Technology Research Insti- tute (ITRI), Taiwan, ...Circuit Design ... See full document
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New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
... VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 × VDD) devices and a silicon-controlled rectifier (SCR) as ... See full document
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PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
... induce the latch-on on V DD ) among the four power-rail ESD clamp circuits are listed in Table ...New power-rail ESD clamp ... See full document
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Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
... cell. The PFET loading tran- sistor pair (ML1 and ML2 in ...devices. The mismatch induced by NBTI and BPTI reduces because high- devices have lower drift, resulting in less Write Half-Select ... See full document
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ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
... view of the conventional diode string with four stacked diodes in CMOS ...view of the four-stage diode string and its parasitic base–emitter tied p-n-p BJTs in a ... See full document
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Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
... efficiency of GGNMOS can not effectively protect the input stage with a thin gate oxide in nanoscale CMOS ...technologies. In this work, a new CDM ESD ... See full document
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