[PDF] Top 20 A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
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A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
... A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, and ... See full document
10
An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension
... Abstract—The video coding standard, H.264/AVC scalable video extension (SVC), adopts various advanced interlayer pre- diction modes to explore the data redundancies between layers ... See full document
12
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
... The H.264/AVC Fractional Motion Estima- tion (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2–6 dB in peak signal-to-noise ...dedicated ... See full document
13
Hardware architecture design of an H.264/AVC video codec
... latest video coding standard. It signifi- cantly outperforms the previous video coding standards, but the extraordi- nary huge computation complexity and memory access requirement make the hardwired codec ... See full document
8
A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications
... an H.264 intra-frame codec IP chip that can be configured as both encoder and ...decoder hardware resources for lower area cost. The design is optimized from algorithm level to ... See full document
12
A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
... Modification for Hardware The algorithm implemented is slightly different from the fast algorithm mentioned ...of hardware design, the available resources allow us to use parallel processing ... See full document
6
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
... an H.264/AVC decoder is the system architecture design with balanced pipelining schedules and proper degrees of ...paper, a hybrid task pipelining scheme is first presented to greatly ... See full document
4
Analysis and architecture design of variable block-size motion estimation for H.264/AVC
... of a searching candidate are generated in the same cycle, and by an adder tree, distortions are accumulated to derive the SAD in one ...provide a high utilization and data reuse, the snake scan is ... See full document
16
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
... designed for the previous stan- dards, where VBS and MRF are not supported, the parameter of our design is set as the single-iteration 4SS with one reference ...dimension for the ...Huang’s ... See full document
10
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC
... contributed a new VLSI architecture for frac- tional motion estimation of ...algorithm for hardware with regular schedule and full ...considerations. ... See full document
4
Algorithm analysis and architecture design for HDTV applications - a look at the H.264/AVC video compressor system
... new H.264/AVC coding standard significantly outperforms previous video coding standards with many new coding ...the high performance comes at a ...to design a ... See full document
10
RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design with On-Demand Data Access
... the video encoder design. In which a low bandwidth and bandwidth aware motion estimation design enables smooth and better video quality as well as lower power consumption ... See full document
12
A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder
... Scalable High Profile Decoder Gwo-Long Li, Yu-Chen Chen, Yuan-Hsin Liao, Po-Yuan Hsu, Meng-Hsun Wen, and Tian-Sheuan Chang, Senior Member, IEEE Abstract—To satisfy the requirement of application hetero- geneities, ... See full document
10
A hierarchical N-queen decimation lattice and hardware architecture for motion estimation
... and Hardware Architecture for Motion Estimation Chung-Neng Wang, Member, IEEE, Shin-Wei Yang, Chi-Min Liu, and Tihao Chiang, Senior Member, IEEE Abstract—A subsampling structure, an ... See full document
12
Projection based adaptive window size selection for efficient motion estimation in H.264/AVC
... quality for a given bit rate, because it may select long mo- tion vectors that need many bits to transmit it also does not help determining how the subdivision should be performed, because the smallest ... See full document
7
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
... HARDWARE ARCHITECTURE DESIGN FOR VARIABLE BLOCK SIZE MOTION ESTIMATION IN MPEG-4 AVC/JVT/ITU-T H.264.. Yu- Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen DSPlIC Design L[r] ... See full document
4
Hardware architecture design for H.264/AVC intra frame coder
... contributed a VLSI architecture design for H.264/AVC intra frame ...using a RISC model to obtain the proper degrees of parallelism under SDTV ...Second, a two-stage ... See full document
4
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications
... Furthermore, if the PERFORMANCE OF CANDIDATE LEVEL DR FOR THE PROPOSED PARALLEL power is very low, we can even support only half-pel or integer- ARCHITECTURE.. pel resolution with one re[r] ... See full document
4
PMRME: A parallel multi-resolution motion estimation algorithm and architecture for HDTV sized H.264 video coding
... The simulation results show that for the threshold voltage variation (AVTH), the constant current the proposed circuit can compensate for AVTH and improve the.. source is difficult to de[r] ... See full document
4
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
... our design and shown in ...in a SW are stored in the SW SRAMs for inter-MB ...while a new row of data are ...only a new row of reference pixels are needed to compute a new search ... See full document
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