[PDF] Top 20 Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
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Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
... HSU: ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION DESIGN WITH SCR-BASED DEVICES IN CMOS INTEGRATED CIRCUITS 247 TABLE I C ... See full document
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Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
... technique with consideration of the gate-oxide reliability issue, is used to provide suitable gate bias to trigger on the SNTSCR device under ESD stress ...condition. On the contrary, this ESD ... See full document
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On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... Terms—Electrostatic discharge (ESD), ESD protection circuit, mixed-voltage I/O circuits, substrate-triggered ...dimensions of MOSFET had been shrunk in the advanced ... See full document
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SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... patents on reliability and quality design for integrated circuits, including 55 ...inventions on ESD protection design and latchup prevention method have been widely used ... See full document
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Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, ...R.O.C., in 1986, 1988, and 1993, respectively. In 1994, he joined the VLSI Design Department of Computer ... See full document
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SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance
... for on-chip protection design against system-level electrical transient disturbance is ...system-level electrostatic discharge (ESD) and electrical fast tran- sient (EFT) tests ... See full document
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Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs
... new on-chip RC-based transient detection cir- cuit is proposed to detect the fast electrical transient under a system-level ESD ...delay in the RC circuit under system-level ESD tests, the ... See full document
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Initial-on ESD protection design with PMOS-triggered SCR device
... NTRODUCTION Electrostatic discharge (ESD) damage has become the main reliability issue for CMOS IC products fabricated in the nanoscale CMOS ...The on-chip ESD ... See full document
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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... substrate of the SCR device, it can be quickly triggered into its latching ...state. In this paper, a novel design concept to turn on the SCR device by applying the ... See full document
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On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
... many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) ... See full document
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Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
... oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products ...Therefore, on-chip ESD protection ... See full document
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A floating gate design for electrostatic discharge protection circuits
... Professor with the Department of Communication Engineering, and an Adjunct Associate Professor at the Institute of Technology Management, ...Director of the Modeling and Simulation Center ... See full document
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An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit
... silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS ...achieved on the gate, drain, and source sides with very few testkey ... See full document
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Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
... ESD protection design, using the stacked-nMOS trig- gered silicon controlled rectifier (SNTSCR) device, has been successfully verified in a ...m CMOS process. The – characteristics of ... See full document
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Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
... voltage on pin, the place- ment of ESD diode from I/O pad to is prohibited, which results in a stringent ESD design challenge for ...time of programming voltage could be as fast as ... See full document
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Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
... advanced CMOS technology applications with the ultra-thin gate oxide, the holding voltage and the on resistance of the PMOS-triggered SCR devices needs to be fur- ther decreased ... See full document
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ESD protection design for CMOS RF integrated circuits using polysilicon diodes
... ESD protection design with stacked polysilicon diodes for RF ICs has been proposed and ...diode with an un-doped central region can be realized in general sub-quarter- micron ... See full document
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A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
... Based upon the understanding of CMOS transient latch-up [lo]-[ 131, the low trigger voltage can be achieved through the proper design of device capaci- tances within [r] ... See full document
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On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation
... Discussion In order to improve the system-level ESD immunity of CMOS ICs, the watchdog timer is often designed with a microelectronic system to regularly check the system abnormal ...itself ... See full document
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Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
... for integrated-circuits products using nanoscale CMOS ...ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified ... See full document
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