第五章 量測結果與性能分析
6.2. 未來發展與待改進之處
6.2.4. 電路模擬時間過長之改進
在設計電路的過程中，我們通常會使用 Hspice 軟體來驗證電路可行性 與正確性。在設計初期對僅含 Netlist 的電路進行前模擬（Pre-simulation），
以驗證電路動作之行為與時序是否合乎預期；在電路設計末期進行後佈局後 模擬（Post-simulation），此時模擬包含佈局時產生的寄生電阻電容等效應，
以驗證實際下線後的可行性。
然而，對一個具有校正功能的十二位元 SA ADC 進行模擬，會碰到模擬 時間過長的問題。在一台不算太老舊的工作站中，以 Cent OS 為作業系統，
進行 Pre-simulation 約耗時兩天，進行 Post-simulation 約耗時四天，這還只是 在取樣 512 點的狀態下。
模擬時間過長的因素之一，為 Hspice 軟體之精準度所致。Hspice 軟體 為業界以及學界公認可信度最高之電路模擬軟體。雖然有很多電路模擬軟體 強調其模擬速度高於 Hspice，如 Ultra-sim 這套軟體便可以針對不同的電路
（類比、數位），設定不同的精準度（類比較詳細、數位較粗略），以達到節 省模擬時間的效果。但是在真正使用後得到的模擬結果，卻是和 Hspice 大 相逕庭。
模擬時間過久對於高解析度、且具有複雜的數位部份之混合信號電路，
無疑是設計上的一大關卡，尤其是對於學習時間有限的碩博士生而言。對於 業界搶攻市場所注重的 Time-to-Market 問題，也是一大阻礙。
或許我們可以使用降低取樣點數目的方式來提升模擬速度。以 12 位元
的 ADC 為例，我們可以先跑幾組模擬，這幾組只有取樣點數分別為 16384、
8192、4096、2048、1024、512 點，其於條件皆相同。我們可以比較這幾筆 資料的模擬結果，在精準度與模擬時間上做取捨。
然而這不是一個能夠治本的方式，當欲設計的 ADC 解析度很高的時 候，採用圖 6-4 的方式，分離類比部份與數位部份於兩不同晶片中，就能有 效提升模擬速度。
類比部份之晶片我們以精準度最高的軟體 Hspice 進行模擬與驗證，以 Awave 軟體觀察各連接點波形；數位部份由於只需驗證功能動作與電路時序 是否正常，則可以用 NC-Verilog 等數位電路模擬軟體進行驗證，以 Nwave 軟體觀察電路時序圖與功能動作圖。如此將兩個不同部份以不同的軟體進行 模擬與驗證，便可有效縮短模擬所需時間。
但是如此一來，便無法進行類比晶片與數位晶片的共同模擬，其下線後 的可信度便會略為降低。但是由於數位部份燒錄在 FPGA 內，若在除錯時發 現，電路整合後性能不佳的原因來自於數位電路，便可以很容易的對數位電 路進行修改、再測試等動作。
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