量測結果總結與比較

表 6.2 整理總結列出了整個資料轉換器對（DAC＆ADC）的效能參數 量測結果。其中動態參數的部份包含了 10GS/s 與 12GS/s 不同取樣訊號頻 率下的結果。

表6. 2 Performance Summary

Item

Specification

Technology

UMC 90nm CMOS Mixed-Mode 1P9M Low-K

Supply voltage

1V

Sampling rate

10GS/s 12GS/s

Resolution

4bits

DNL (LSB)

DAC: -0.10 ~ 0.08

Effective Resolution

Bandwidth (ERBW)

> 2.58GHz > 3.14GHz

DAC 83.8 mW

ADC 215.4 mW

DAC + ADC 299.2mW

Power Dissipation

of the Test Chip

from the 1V supply

Total (including the

DfT circuits) 322.8mW

將我們設計的DAC 與近幾年的知名國際期刊或會議論文上的幾篇同為 超高速的 DAC 作一比較，如表 6.3 所示。由於通常單一 DAC 的設計較少 會有低於6bits 解析度的設計，因此表 6.3 的其他比較對象都以相同為數 GS/s 取樣率的DAC 為主。可以看出我們設計的 DAC 具有最高的轉換速率，在 高達12GS/s 的取樣轉換能力之下，僅消耗約 83.8mW 的功率。且以消耗功 率與取樣頻率之比值（Power/GHz）作為能量效益（energy efficiency）的比 較基準，可看出我們的設計是裡面中最低的，只有6.98pJ。

表6. 3 Benchmark of the DAC

Sources

Item

ISSCC 2001 JSSC 2001

[54][55]

JSSC 2004 [56] Sample

Rate

8 GS/s 0.8 GS/s 3 GS/s 10 GS/s

12 GS/s Resolution

8 bits 9 bits 6 bits 4 bits

4 bits Technology

0.25μm

CMOS

Supply

Voltage

2.5V 3.3V 1.2V 1.2V

1V

SNDR

N/A N/A N/A > 25.0 dB @

Fin=1.11GHz

> 26.02 dB

@ F

in

=1.33GHz

SFDR

N/A 55 dBc @

low freq.

36.2 dBc @ Fin=1.43GHz

> 27.3 dBc

@ Fin=1.11GHz

> 33.55 dBc

@ F

in

=1.33GHz

Power

1900 mW 174 mW 29 mW 142 mW

83.8 mW

Power/GHz

237.5 pJ 217.5 pJ 9.67 pJ 14.2 pJ

6.98 pJ

另外也將我們設計的ADC 與近幾年知名國際期刊或會議論文上的幾篇 同為超高速且4~6 位元解析度的 ADC 相比較，如表 6.4 所示。可看出我們 的設計能夠在pure CMOS 的製程下，不使用 time-interleaving 的架構而達到 10GS/s 甚至 12GS/s 的超高速。同樣以 Power/GHz 的能量效益比作比較，

我們設計的ADC 也是裡面中最低的，每 GHz 只耗用掉 17.95pJ 的能量。

表6. 4 Benchmark of the ADC

Sources

Item

VLSI Ckt 2007 [58]

CICC 2007 [59]

ISSCC 2006 JSSC 2007 Sample

Rate

3.5 GS/s 4.2 GS/s 4 GS/s 10 GS/s

12 GS/s Resolution

6 bits 5 bits 4 bits 4 bits

4 bits Technology

90nm

CMOS

Supply

Voltage

0.9V 1.2V A: 1.8V Fin=100MHz

> 25.0 dB @ Fin=1.11GHz

> 26.02 dB

@ F

in

=1.33GHz SFDR

38.67 dBc

F

in

=1.33GHz ERBW

1.75 GHz 1.75 GHz 0.9 GHz > 1.6 GHz

> 3.16 GHz

Power

98 mW 180 mW ³ 619 mW 210 mW

215.4 mW Power/GHz

28 pJ 42.86 pJ 154.8 pJ 21 pJ

17.95 pJ

FOM

¹ 0.95²

pJ/step 2.8 pJ/step 23.2 pJ/step < 4.10 pJ/step

< 2.07 pJ/step

1:

ERBW

Power FOM

_{ENOB DC}

2

3: excluding the output buffers

第七章

結論與未來展望

本論文提出並設計了一組應用於前瞻串列式連結（Advanced Serial Link）收發機之超高速資料轉換器對（DAC & ADC）。在取樣率高達10GS/s 且解析度為4bits 的設計目標下，DAC 使用 Current-steering 的架構作設計，

其數位電路的核心使用電流式邏輯（CML）電路來設計製作。CML 除了適 合於低電壓的設計環境之外，也可達到最高速的切換能力並同時降低高速 轉換下容易發生的power-ground bounce 問題。而關鍵的輸出電流源電路使 用高頻響應較佳的開關疊接電流源電路（SCCS），能有效提升電流源高頻 時的輸出阻抗。且為了克服訊號轉換的延遲時間大於取樣訊號半週期時間

（50ps）的問題，在 DAC 的取樣時脈訊號路徑上使用數個 clock buffers 建 立waveform pipeline 機制，使過短的取樣訊號半週期時間問題可獲得解決。

另一方面，ADC 的設計使用 Flash 的架構，以多級（multi-stage）主動式負 回授前置放大器（Active negative feedback Pre-Amplifier）串接來完成整個 寬頻比較器的設計。且藉由分析多級串接前置放大器的設計級數與功率消 耗之關係來達到最佳功率消耗效益的設計結果。ADC 編碼器的數位電路部 份也都使用CML 的邏輯電路作設計，且編碼器為 Gray code 編碼方式的設 計，利用Gray code 的特性可降低因比較器發生 metastable 現象而發生的編 碼錯誤。同樣為了解決訊號propagation delay 的時間過大，在 ADC 的取樣 時脈訊號路徑上相同使用了waveform pipeline 的技巧，使 Latch 電路能正確 的擷取並儲存正確的資料。為了完成超高速DAC 及 ADC 的測試，我們加 入了輔助測試的DfT 電路，以 ADC 串接 DAC 形成 digital loopback 的組態，

以完成全速運作下的量測。同時 DfT 的電路也提供了 Eye Diagram 測試模 式，可檢視評估此組資料轉換器對應用於串列式傳輸系統中，最大所能達 到的位元傳輸率。

以UMC 90nm CMOS Mixed-Mode 1P9M Low-K 製程製作的實驗晶片 之量測結果顯示，DAC 的 DNL 都小於±0.10LSB，INL 則不超過±0.12LSB。

ADC 之 DNL 介於±0.27LSB，INL 在±0.25LSB 以內。在 10GS/s 的取樣頻率 下，輸入1.111GHz 的 sinusoidal 訊號，輸出訊號之頻譜結果可得到 27.0 dB 的SNR、25.9 dB 的 SNDR 以及高達 34.9 dBc 的 SFDR 之動態參數結果，

此時 SNDR 對應到的 ENOB 可達到 4bits。串接後的整個資料轉換器對之 ERBW 可超過 2.5GHz。若再經 DAC 之 ZOH 效應的補償後，可檢視出單獨 ADC 最差可能之 ERBW 可超過 2.6GHz。量測結果也顯示電路具備能操作 在 12GS/s 的更高取樣頻率，在 12GS/s 時的量測結果顯示，輸入 1.33GHz 的sinusoidal 訊號，輸出的 SNR 為 26.9 dB，SNDR 為 26.0 dB 而 SFDR 可 高達33.6 dBc，且 ENOB 也可達到 4bits 的解析度。12GS/s 時的 ERBW 可 超過 3GHz 的輸入訊號頻寬，單獨 ADC 最差可能之 ERBW 則可超過 3.16GHz。而 Eye Diagram 的量測結果顯示，當 clock rate 為 2.5Gbps 之時，

DAC 輸出之 Eye Diagram 仍可清楚地分辨出 16 個不同的準位，說明此資料 轉換器對確實能應用於 16-PAM 的晶片系統串列傳輸連結，且此時相對應 的等效位元傳輸率可高達10

Gbps

的超高速。在供應電壓源為1V 的情況下，

DAC 與 ADC 分別消耗約 83.8mW 與 215.4mW 的功率。整個測試晶片包含 DfT 電路共消耗約 322.8mW。

對於 10GS/s 的 ADC 而言，理論上應要能達到 5GHz 的 ERBW，但由 於缺乏能夠處理10GHz 取樣訊號以及使用 CMOS 製程製作的取樣保持電路

（Sample-and-Hold circuit），使得 ADC 能達到的頻寬受到限制。目前雖然 有超高速ADC 整合保持電路的設計[16]，但其使用 time-interleaved 的方式

來達成高速的取樣轉換率，且使用SiGe 等較昂貴的製程製作，且動輒消耗 數瓦（Watt）的功率。而且 ERBW 也依然無法達到理論上的結果。現階段 以 CMOS 製程所設計的超高速取樣保持電路已有所文獻[60]可供參考，但 真正將此類超高速的取樣保持電路整合進高速ADC 的設計卻相對較少，且 整合之後卻也容易遇到其他方面的問題。未來針對超高速ADC 的設計，若 是能逐一克服CMOS 製程設計上的這些困難，將可以應用在我們的設計當 中，使效能可更趨完善。

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在文檔中 以90奈米CMOS製程設計一應用於前瞻串列式連結收發機之超高速資料轉換器對 (頁 131-0)