Issue of Mixed-Voltage I/O Interface

To improve circuit operating speed and performance, the device dimension of MOSFET has been shrunk in the advanced CMOS ICs. With the scaled-down device dimension in advanced CMOS technology, the power supply voltage is also scaled down to reduce the power consumption and to meet the gate-oxide reliability. However, most microelectronic systems nowadays consist of mix semiconductor chips fabricated in different CMOS technologies. Therefore, the microelectronic systems often require the interfaces between

semiconductor chips or sub-systems which have different internal power supply voltages.

With the different power supply voltages in a microelectronic system, chip-to-chip I/O interface circuits must be designed to avoid electrical overstress across the gate oxide [9], to avoid hot-carrier degradation [10] on the output devices, and to prevent the undesired leakage current paths between the chips [11], [12]. For example, a 3.3-V I/O interface is generally required by the ICs realized in CMOS processes with the normal internal power-supply voltage of 2.5V or 1.8V. The traditional CMOS I/O buffer with VDD of 2.5V is shown in Fig.

1.3(a) with both output and input stages. When an external 3.3-V signal is applied to the I/O pad, the channel of the output pMOS and the parasitic drain-to-well junction diode in the output pMOS cause the leakage current paths from the I/O pad to VDD, as the dashed lines shown in Fig. 1.3(a). Moreover, the gate oxides of the output nMOS, the gate-grounded nMOS for input electrostatic discharge (ESD) protection, and the input inverter stage are over-stressed by the 3.3-V input signal to suffer the gate-oxide reliability issue. By using the additional thick gate-oxide process (or called as dual gate-oxide CMOS process [13], [14]), the gate-oxide reliability issue can be avoided. However, the process complexity and fabrication cost are increased.

To solve the gate-oxide reliability issue without using the additional thick gate-oxide process, the stacked-MOS configuration has been widely used in the mixed-voltage I/O circuits [15]-[21]. The typical 2.5V/3.3V-tolerant mixed-voltage I/O circuit is shown in Fig.

1.3(b) [16]. The independent control on the top and bottom gates of stacked-nMOS device allows the devices to meet reliability limitations during normal circuit operation. The gate of top nMOS in the stacked-nMOS device is biased at VDD (e.g. 2.5V in a 2.5V/3.3V mixed-voltage I/O interface). The gate of bottom nMOS is biased at VSS by the pre-driver circuit to avoid leakage current through the stacked-nMOS structure, when the I/O circuit has a high-voltage input signal. With a high-voltage input signal at the pad (e.g. 3.3V in a 2.5V/3.3V mixed-voltage I/O interface), the common node between the top nMOS and bottom nMOS in the stacked-nMOS structure has approximately a voltage level of VDD-Vth (~ 1.9V), where Vth (~ 0.6V) is the threshold voltage of nMOS device. Therefore, the stacked-nMOS can be operated within the safe range for both dielectric and hot-carrier reliability limitations. The pull-up pMOS, connected from the I/O pad to the VDD power line, has the gate tracking circuits for tracking the gate voltage and the n-well self-biased circuits for tracking n-well voltage, which are designed to ensure that the pull-up pMOS does not

conduct current when the 3.3-V input signals enter the I/O pad. In such mixed-voltage I/O circuits, the on-chip ESD protection circuits will meet more design constraints and difficulty.

The ESD protection design of I/O pad cooperating with power-rail ESD clamp circuit is shown in Fig. 1.4(a), where a PS-mode ESD pulse is applied to the I/O pad. ESD current at the I/O pad under the PS-mode ESD stress can be discharged through the parasitic diode of pMOS from I/O pad to VDD and the VDD-to-VSS ESD clamp circuit to ground. But, due to the leakage current issue in the mixed-voltage I/O circuits, there is no diode connected from the I/O pad to VDD power line in the mixed-voltage I/O circuits. Without the diode connected from the I/O pad to VDD in the mixed-voltage I/O circuits, the ESD current at I/O pad under PS-mode ESD stress cannot be discharged from the I/O pad to VDD power line, and cannot be discharged through the additional VDD-to-VSS ESD clamp circuit. Therefore, the power-rail ESD clamp circuit did not help to pull up ESD level of the mixed-voltage I/O pad under the PS-mode ESD stress. The ESD current path in the mixed-voltage I/O circuits with power-rail ESD clamp circuit under PS-mode ESD stress in illustrated in Fig. 1.4(b).

Such ESD current at the I/O pad is mainly discharged through the stacked-nMOS by snapback breakdown. However, the nMOS in stacked configuration has a higher trigger voltage and a higher snapback holding voltage, but a lower secondary breakdown current (It2), as compared to that of the single nMOS [22], [23]. Therefore, such mixed-voltage I/O circuits with stacked nMOS often have much lower ESD level for under PS-mode ESD stress, as compared to the traditional I/O circuits with a single nMOS [22]. In addition, without the diode connected from the I/O pad to VDD, the mixed-voltage I/O circuit also has a lower ESD level for I/O pad under PD-mode ESD stress. The absence of the diode between I/O pad and VDD power line in the mixed-voltage I/O circuits will seriously degrade ESD performance of the I/O pad under the PS-mode and PD-mode ESD stresses. By using extra process modification such as ESD implantation, the ESD robustness of stacked-nMOS device can be further improved [24], [25], but the process complexity and fabrication cost are increased. In addition, the induced high voltage on the gate of top nMOS transistor under ESD stress will cause high-current crowding effect in the channel region to seriously degrade ESD robustness of stacked-nMOS device in the mixed-voltage I/O circuits [26]. Therefore, effective ESD protection design without increasing process complexity is strongly requested by the mixed-voltage I/O circuits in the scaled-down CMOS processes. In this thesis, the substrate-triggered stacked-nMOS device, which combines the substrate-triggered technique with the stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of

CMOS ICs [27].