New ESD Protection Schemes for IC with Power-Down-Mode Operation 45

For IC with power-down-mode operation, the on-chip ESD protection circuits will meet more design constraints and difficulties. In this chapter, three new ESD protection schemes for CMOS IC with power-down-mode operation are proposed. By adding a VDD ESD bus line and diodes, the ESD protection design can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the ESD protection design has no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. These new ESD protection designs for IC with power-down-mode operation has been successfully designed and verified in a 0.35-µm silicided CMOS process [31]-[33].

Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition [33].

3.1 New ESD Protection Schemes for IC with Power-Down-Mode Operation

3.1.1 ESD Protection Scheme I

The proposed ESD protection scheme I for the IC with power-down-mode operation is shown in Fig. 3.1 with the additional ESD bus line (VDD_ESD), which is realized by wide metal line in CMOS IC. The VDD_ESD bus line is not directly connected to an external power supply pin. The diode D1 is connected between the VDD power line and VDD_ESD bus line to block the leakage current path from the input pad to VDD when the power of VDD is off. The diode D2 is connected between the VDD power line and the source of output

power of VDD is off. The VDD_ESD bus line is not connected to the source of Mp_out in this scheme, because Mp_out may be turned on. The gate voltage of Mp_out will be dropped down and induces leakage current between I/O pads when the power of VDD is off. With the new proposed ESD protection scheme, the leakage current or malfunction issues for the IC with power-down-mode operation can be avoided. The diode D3 is connected between the output pad and VDD_ESD bus line for ESD protection purpose. One power-rail ESD clamp circuit is connected between VDD power line and VSS power line. A second power-rail ESD clamp circuit is connected between VDD_ESD bus line and VSS power line.

In the typical mixed-voltage I/O buffer, the output pMOS, connected from the I/O pad to the VDD power line, has self-biased circuits for tracking its gate and n-well voltages to avoid the leakage current path from the I/O pad to VDD when an over-VDD external signal is applied to the I/O pad [16]. However, during the power-down-mode operation, the tracking circuits will not function because the power of VDD is off. The channel of output pMOS cannot be kept off when the external voltage level on the output pad is high; therefore the leakage current may be induced from the output pad to VDD when the power of VDD is off.

By using the new proposed ESD protection scheme, the leakage current path from the I/O pad to VDD can be completely blocked by the diode D2 during the power-down-mode operation.

Although the output signal cannot be pulled up to VDD (kept at VDD-Vd, where Vd is the cut-in voltage of the diode D2) during normal circuit operating condition, it can be further improved with additional output-swing improvement circuit.

The ESD current discharging paths of the input pad under PS-mode ESD stress condition, the output pad under PS-mode ESD stress condition, the input pad under PD-mode ESD stress condition, and the output pad under PD-mode ESD stress condition are shown in Figs. 3.2(a)

~ 3.2(d), respectively. The ESD current at the input (or output) pad under PS-mode ESD stress can be discharged through the parasitic diode of Mp_in (or the diode D3) to the VDD_ESD bus, and then through the ESD clamp circuit from the VDD_ESD bus to the grounded VSS power line. The ESD current at the input (or output) pad under the PD-mode ESD stress can be discharged through the parasitic diode of Mp_in (or the diode D3) to VDD_ESD bus line, the ESD clamp circuit to VSS power line, and then through the parasitic diode of ESD clamp circuit to the grounded VDD power line. The negative ESD current at the input (or output) pad under the NS-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to ground. The negative ESD current at the input (or output) pad under the ND-mode ESD stress can be discharged through the parasitic diode of Mn_in (or

Mn_out) to VSS power line, and then discharged through the VDD-to-VSS ESD clamp circuit to the grounded VDD power line. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed ESD protection scheme.

3.1.2 ESD Protection Scheme II

The proposed ESD protection scheme II for the IC with power-down-mode operation is shown in Fig. 3.3. The design concept is similar to that of the ESD protection scheme I. In ESD protection scheme II, the VDD_ESD bus line is separated into input stage and output stage by the diode D3. The VDD ESD bus line of output stage is connected to the source of output pMOS (Mp_out). The diode D1 is connected between the VDD power line and VDD_ESD bus line to block the leakage current path from the input pad to VDD when the power of VDD is off. The diode D2 is connected between the VDD power line and the source of Mp_out to block the leakage current path from the output pad to VDD when the power of VDD is off. The gate voltage of Mp_out will be dropped down to induce leakage current between I/O pads when the power of VDD is off. The diode of D3 is used to block the leakage current between the I/O pads. One power-rail ESD clamp circuit is connected between VDD power line and VSS power line. A second power-rail ESD clamp circuit is connected between VDD_ESD bus line and VSS power line.

The ESD current at the input (or output) pad under PS-mode ESD stress can be discharged through the parasitic diode of Mp_in (or Mp_out) to the VDD_ESD bus, (the diode of D3,) and then discharged through the power-rail ESD clamp circuit from the VDD_ESD bus to the grounded VSS power line. The ESD current at the input (or output) pad under the PD-mode ESD stress can be discharged through the parasitic diode of Mp_in (or Mp_out) to VDD_ESD bus line, (the diode of D3,) the power-rail ESD clamp circuit to VSS power line, and then through the parasitic diode of power-rail ESD clamp circuit to the grounded VDD power line.

The negative ESD current at the input (or output) pad under the NS-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to ground. The negative ESD current at the input (or output) pad under the ND-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to VSS power line, and then discharged through the power-rail ESD clamp circuit to the grounded VDD power line. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed ESD protection scheme.

3.1.3 ESD Protection Scheme III

The proposed ESD protection scheme III for the IC with power-down-mode operation is shown in Fig. 3.4. The design concept is similar to that of the ESD protection scheme I. The diode D1 is connected between the VDD power line and VDD ESD bus line to block the leakage current path from the input or output pad to VDD, when the power of VDD is off.

The diode D3 in scheme II is replaced by the Mp1 in scheme III to block the leakage current between the I/O pads when the power of VDD is off. The gate of Mp1 is connected to the VDD power line. Therefore, Mp1 is turned off under the normal circuit operating condition.

Under power-down-mode operating condition, Mp1 is turned on to keep the Mp_out off. In addition, the power line of the pre-driver internal circuits which controlled the gate of Mp_out is connected to the VDD ESD bus line to avoid the leakage current from the pre-driver internal circuits to VDD power line, when the power of VDD is off. The ESD current at the input (or output) pad under PS-mode ESD stress condition can be discharged through the parasitic diode of Mp_in (or Mp_out) and the power-rail ESD clamp circuit between the VDD ESD bus line and the VSS power line to ground. The ESD current at the input (or output) pad under the PD-mode ESD stress condition can be discharged through the parasitic diode of Mp_in (or Mp_out) to VDD ESD bus line, the power-rail ESD clamp circuit to VSS power line, and then the parasitic diode of ESD clamp circuit to the grounded VDD power line. The negative ESD current at the input (or output) pad under the NS-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to ground. The negative ESD current at the input (or output) pad under the ND-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to VSS power line, and then discharged through the power-rail ESD clamp circuit to the grounded VDD power line. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed ESD protection scheme.

Therefore, with the new proposed ESD protection schemes, the leakage current or malfunction issues for the IC with power-down-mode operation can be avoided. The internal circuits of CMOS IC can be fully protected against ESD damage by the new proposed ESD protection schemes.

3.1.4 Layout Consideration

For saving the layout area, the VDD_ESD bus line in the proposed ESD protection schemes can be realized by the different parallel metal layer, which overlaps the VDD power

line. The junction perimeter of the diodes (D1, D2, and D3) in the proposed ESD protection schemes can be drawn with small layout area, because the ESD current is discharged through these diodes with the forward-diode path. The device dimension of Mp1 in scheme II can be adjusted with less impact on ESD performance. In addition, it’s important to note that the location of power-rail ESD clamp circuit connected between VDD_ESD bus line and VSS power line is an important factor to implement the ESD protection scheme II. Because the ESD bus line is separated into input stage and output stage by the diode D3, the power-rail ESD clamp circuit must be placed in the input stage to provide the ESD current discharging path for input pad under ESD stress.

3.2 Experimental Results

The testchip with traditional and new proposed ESD protection schemes had been fabricated in a 0.35-µm silicided CMOS process. Fig. 3.5 shows the layout view of the new proposed ESD protection scheme I. Some inverters are connected from the input pad to the output pad, being served as the internal circuits for function verification of this testchip. The input ESD protection devices are realized by the gate-connected-to-source pMOS and gate-grounded nMOS with both the device dimensions (W/L) of 490/0.5 (µm/µm). The output ESD protection devices are realized by the output buffer of pMOS and nMOS with the same device dimensions. The layout parameters of ESD protection devices and output buffers are drawn according to the foundry’s ESD rules with the silicide-blocking mask. In the proposed ESD protection schemes, the junction perimeter of the diodes (D1, D2, and D3) is drawn as 50µm. In the proposed ESD protection scheme III, the device dimension (W/L) of Mp1 is drawn as 20/0.5 (µm/µm). The power-rail ESD clamp circuit is realized by the substrate-triggering field-oxide device (STFOD) [76], [77] to have high enough ESD level in a limited layout area, as shown in Fig. 3.6. The device dimensions for the power-rail ESD clamp circuit are drawn as R=55.3kΩ, C=14.2pF, W/L of Mp=100µm/1.2µm, W/L of Mn=20µm/1.2µm, and W/L of STFOD=232.8µm/1µm.

3.2.1 Leakage Current

The leakage currents at the input pad of the traditional and new proposed ESD protection

current is measured by applying a voltage ramp from 0 to 3.3V to the input pad under the bias condition of 3.3-V VDD and 0-V VSS. In Fig. 3.7(a), the leakage currents at the input pad of traditional ESD protection scheme, new proposed ESD protection schemes I, II, and III are 109pA, 134pA, 132pA, and 122pA, respectively, with a 3.3-V signal applying to the input pad. From the measured results, the new proposed ESD protection schemes do not induce any extra leakage current under normal circuit operating condition.

The leakage currents at input pad and output pad of the traditional and new proposed ESD protection schemes under power-down-mode operating condition are measured and compared in Figs. 3.7(b) and 3.7(c), respectively. The leakage current is measured by applying a voltage ramp from 0 to 3.3V to the input or output pad under the bias condition of 0-V VDD and 0-V VSS. From the measured results, the leakage currents at the input pads (output pads) of the new proposed ESD protection schemes are only ~130pA in Fig. 3.7(b) (~300pA in Fig.

3.7(c)), when a 3.3-V signal is applied to the input pad (output pad). On the contrary, the traditional ESD protection scheme has a very high leakage current of up to several mA when the input or output voltage is only increased to 0.7V. The leakage current in the new proposed ESD protection scheme has been successfully blocked by the diode of D1 or D2. The experimental results have verified that the new proposed ESD protection schemes can avoid the leakage current from the I/O pin to VDD power line under the power-down-mode operating condition.

3.2.2 Function Verification

The measurement setup to verify the function of I/O cells with the new proposed ESD protection schemes, or the traditional ESD protection scheme, under normal circuit operating condition and power-down-mode operating condition is shown in Fig. 3.8. To verify the function among the different designs under normal circuit operating condition, a 0-to-3.3 V voltage pulse with a rise time of 20 ns is applied to the input pad under the bias condition of 3.3-V VDD and 0-V VSS. In addition, to verify the function among the different designs under power-down-mode operating condition, a 0-to-3.3 V voltage pulse with a rise time of 20 ns is applied to the input pad under the bias condition of 0-V VSS but VDD is floating.

Figs. 3.9(a) and 3.9(b) show the voltage waveforms on the input/output pad of the I/O cells with the traditional ESD protection scheme under normal circuit operating condition and power-down-mode operating condition, respectively. As shown in Fig. 3.9(a), the I/O cells

operating condition. However, under the power-down-mode condition, the voltage waveform on the output pad is dropped to a voltage level of ~1.4V, when the input voltage level is 0V, as that shown in Fig. 3.9(b). It implies that the internal circuits are triggered by the input voltage waveform under power-down-mode operating condition, although the circuits are expected to be off. With the wrong voltage waveform at the I/O pads, the system could be malfunction.

Figs. 3.10(a) and 3.10(b) show the voltage waveforms on the input/output pad of the I/O cells with the new proposed ESD protection scheme I under normal circuit operating condition and power-down-mode operating condition, respectively. As shown in Fig. 3.10(a), the I/O cells with the new proposed ESD protection scheme I can be operated normally under normal circuit operating condition. The high voltage level on the output pad is kept at ~2.7V (VDD-Vd, where Vd is the cut-in voltage of the diode D2). In Fig. 3.10(b), the voltage level on the output pad is always kept at ~ 0V under power-down-mode operating condition. This result has verified that the internal circuits can be really kept inactive by the new proposed ESD protection scheme I under power-down-mode operating condition. In addition, the measured voltage waveforms on the input/output pad of I/O cells with the proposed ESD protection scheme II or ESD protection scheme III have the same results as those shown in Figs. 3.10(a) and 3.10(b) under normal circuit operating condition and power-down-mode operating condition, respectively. The experimental results have verified that the I/O cells with the proposed ESD protection scheme II or ESD protection scheme III can be normally operated under normal circuit operating condition, as well as the internal circuits can be really kept inactive under power-down-mode operating condition.

3.2.3 ESD Robustness

The HBM ESD robustness of I/O pads with the traditional or new proposed ESD protection schemes under different pin combinations is listed in Table 3.1. The failure criterion is defined as the leakage current of the circuits after ESD stress is greater than 1µA under the normal operating voltage of 3.3V. With the traditional ESD protection scheme, the ESD level of the I/O pads is 5kV, which is dominated by the I/O pad under the ND-mode ESD stress or positive VDD-to-VSS ESD stress. However, with the new proposed ESD protection scheme I, II and III, the ESD level of the I/O pads is 7.5kV, which is dominated by the I/O pad under the PS-mode or PD-mode ESD stress. The ESD level of I/O pad under the

in the new proposed ESD protection scheme, which is discharged through the diode D1 and power-rail ESD clamp circuit between the VDD ESD bus line and VSS power line. As a result, ESD level of the whole chip can be efficiently improved by the new proposed ESD protection schemes for IC with power-down-mode operation.