Stacked-NMOS with Substrate-Triggered Technique

2.2.1 Substrate-Triggered Stacked-NMOS Device

The snapback operation of stacked-nMOS device depends on the substrate current (Isub), which is created at the reverse-biased drain/substrate junction, to forward bias the source/substrate junction. Hence, the substrate resistance (Rsub) and substrate current (Isub) are the important design parameters for ESD protection [73], [74]. However, the substrate-triggered technique [56]-[58] can be used to generate the substrate current. With the substrate-triggered current, the trigger voltage of the stacked-nMOS device in mixed-voltage I/O circuits can be reduced for more effective ESD protection. In this work, the substrate-triggered stacked-nMOS device, which combines the substrate-triggered technique with the stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs.

The finger-type layout pattern and the corresponding cross-sectional view of the new proposed substrate-triggered stacked-nMOS device are shown in Fig. 2.3(a) and Fig. 2.3(b), respectively. As shown in Fig. 2.3, an additional p+ diffusion is inserted into the center drain region of stacked-nMOS device as the substrate-triggered point. The trigger current (Itrig) is provided by the substrate-triggered circuit. An n-well structure is further diffused under the source region, which is also surrounding the whole device, to form a higher equivalent substrate resistance for improving turn-on efficiency of the parasitic lateral bipolar transistor in the stacked-nMOS device.

2.2.2 ESD Protection Circuit

The ESD protection design, which includes the substrate-triggered stacked-nMOS device and the substrate-triggered circuit for the mixed-voltage I/O circuits, is shown in Fig. 2.4. The substrate-triggered circuit is composed of the diode string, a pMOS Mp1, and an nMOS Mn1, to provide the substrate current for triggering on the parasitic lateral bipolar transistor in the stacked-nMOS device while the ESD voltage is applied on the I/O pad. The anode of the diode string in the substrate-triggered circuit and the collector of the parasitic bipolar

string is connected to the source of Mp1. The emitter (the base) of the lateral bipolar transistor is connected to the VSS power line (the drain of Mp1). The nMOS Mn1 is connected between the base of the lateral bipolar transistor and the VSS power line. The gates of Mp1 and Mn1 are connected together to the VDD power line through a resistor. The resistor is realized by an n+ diffusion with a parasitic n+/p-sub diode to avoid the antenna effect during the CMOS process fabrication. The diode string including in the substrate-triggered circuit is composed of individual diodes formed by using P+ diffusion in the separated n-well structure. The total voltage drop across the diode string can be expressed as [64]:

Vstring = total voltage drop across the m diodes,

m= the number of diodes in the diode string, n= ideality factor, and

β= the beta gain of the parasitic vertical pnp bipolar transistor in the diode structure.

During the ESD stress condition, the Mp1 is used in conjunction with the diode string to provide the substrate current to trigger the parasitic lateral bipolar transistor in the stacked-nMOS device. Once the lateral bipolar transistor in the stacked-nMOS device has been turned on, the ESD current is discharged from the I/O pad to VSS.

2.2.3 Operating Principles

Fig. 2.5 shows the cross-sectional view of the substrate-triggered stacked-nMOS device with the substrate-triggered circuit for protecting mixed-voltage I/O circuits. In the normal circuit operating condition, the substrate-triggered circuit should remain in a non-conductive state, so that it does not interfere with the voltage levels on the I/O pad. For the 2.5V/3.3V mixed-voltage IC application, 3.3V tolerance was desired for normal circuit operation with a 2.5-V VDD supply in the chip. The turn-on voltage of the substrate-triggered circuit roughly equals to Vpad ≧ V^string(I)+|Vtp|+VDD, where the Vtp is the threshold voltage of the pMOS Mp1. The turn-on voltage can be adjusted by varying the numbers of the diodes in the diode string. To satisfy the requirement in the 2.5V/3.3V mixed-voltage application, the number of

the diodes in the diode string should be adjusted to let the turn-on voltage greater than 3.3V.

When the I/O pad is applied with a high input voltage of 3.3V, Mp1 is still kept off, and the local substrate of the stacked-nMOS is biased at VSS by the turned-on Mn1. With the diode string to block the 3.3V input voltage on the I/O pad, the Mp1 with thin gate oxide has no gate-oxide reliability issue during the normal circuit operating condition.

The choice of a particular diode string is also determined by the specified pin leakage current at a given temperature. If a lower input leakage is desired, the numbers of the diodes in the diode string should be increased. Since the diode string is not the main ESD current discharge path, its perimeter can be adjusted with less impact on ESD performance. The leakage current problem of the diode string comes from the parasitic vertical pnp bipolar transistor of each diode formed by the P+ diffusion in an n-well. The Mp1 in conjunction with a diode string is used to reduce the leakage current at the I/O pad in the normal operating condition. Moreover, the Mn1 with its gate biased at VDD is always turned on to bypass any leakage current, which may trigger on the lateral npn bipolar transistor in the normal circuit operating condition.

Under the PS-mode ESD stress condition, the gate of the Mp1 has an initial voltage level of ~0V, while the VSS pin is grounded but the VDD pin is floating. The substrate-triggered circuit will provide the trigger current flowing through the diode string and the Mp1 into the p-substrate, when Vpad ≧ Vstring(I)+ |Vtp|. For a given Rsub, the substrate-triggered circuit must supply an enough trigger current (Itrig) to raise up the local substrate potential, so that VBE (= Isub x Rsub) > 0.6V for triggering on the parasitic lateral n-p-n bipolar transistor in the stacked-nMOS device. Once the lateral bipolar transistor is turned on, the ESD current is discharged from the I/O pad through the lateral bipolar transistor to the grounded VSS. The trigger current provided by the substrate-triggered circuit is determined by the diode string and the size of Mp1. With an appropriate trigger current, the substrate potential is raised up to trigger on the lateral bipolar transistor and to reduce the trigger voltage of the ESD protection circuit. Therefore, ESD robustness of the mixed-voltage I/O circuits with the stacked-nMOS device can be effectively improved by this new proposed substrate-triggered design. It is important to note that the device size of Mp1 should be large enough than that of Mn1 to provide efficient trigger current into the p-substrate for triggering parasitic lateral n-p-n bipolar transistor. Partial trigger current could be flowed through the Mn1 into VSS power line due to the transient coupling voltage on the gate of Mn1 during PS-mode ESD stress condition. In this work, the device ratio of Mp1 to Mn1 is 5.

A modified connection on the ESD protection design with the substrate-triggered stacked-nMOS device to protect the mixed-voltage I/O circuits is shown in Fig. 2.6. The substrate-triggered circuit is connected from the self-biased n-well of the pull-up pMOS, where the parasitic drain-well diode Dp between the I/O pad and the n-well essentially exists in the pMOS device structure. Under the PS-mode ESD stress condition, the trigger current flows through the parasitic diode Dp and the substrate-triggered circuit to raise the local substrate potential for triggering on the lateral bipolar transistor in the stacked-nMOS device.

The main purpose of this modified connection on the ESD protection circuit is to provide the mixed-voltage I/O buffer with a higher ESD robustness but no extra additional capacitance (generating from the ESD detection circuit) to the I/O pad. This modified design is more suitable for high-speed I/O applications, which often require a lower input loading capacitance to the I/O pad.