CHAPTER 4 ESD PROTECTION DESIGN IN HIGH-VOLATGE
4.3 Design of Latchup-Free Power-Rail ESD Clamp Circuits
4.3.3 Latchup-Free Power-Rail ESD Clamp Circuits
The proposed power-rail ESD clamp circuits with two cascaded FOD devices and three cascaded FOD devices in high-voltage CMOS ICs are shown in Figs. 4.15(a) and 4.15(b), respectively. The substrate-triggered technique is achieved by the RC-based ESD detection circuit [76]. The trigger voltage of stacked FOD devices can be decreased to quickly discharge ESD current by the substrate-triggered technique [76]. The latchup immunity of power-rail ESD clamp circuit to the noise transient can be highly increased by the stacked-field-oxide structure. By adjusting different numbers or even different types of stacked ESD devices (NMOS, SCR, or FOD) in the power-rail ESD clamp circuits, the total holding voltage of the stacked structure can be designed higher than the supply voltage.
Therefore, the transient-induced latchup issue can be successfully overcome without modifying the high-voltage CMOS process. Latchup-free power-rail ESD clamp circuit can be achieved for the IC applications with power supply of 40V.
4.4 Summary
Latchup or latchup-like issue of ESD protection devices in high-voltage CMOS ICs has been clearly investigated by TLP stress and TLU test. The impact of low holding voltage of
danger during normal circuit operating condition has been shown. By adjusting different numbers or different types of stacked ESD devices in the power-rail ESD clamp circuits, the total holding voltage of the stacked structure can be designed higher than the supply voltage without using extra process modification in the high-voltage CMOS technology. For the IC applications with power supply of 40V, a new latchup-free power-rail ESD clamp circuit with stacked-field-oxide structure has been designed and successfully verified in a 0.25-µm 40-V CMOS process to meet the desired ESD level.
Voltage (V)
Fig. 4.1 The TLP-measured I-V characteristics of (a) DDD MOS structure fabricated in a 0.35-µm 18-V CMOS process and (b) LDMOS structure fabricated in a 0.25-µm 40-V CMOS process.
NBL N-well STI
Gate Drain
Source
P-well
P-sub
N+
N+
(a)
NBL N-well STI
Gate Drain
Source
P-well
P-sub
N+
N+
(b)
Fig. 4.2 Simulated current distributions in the 40-V nMOSFET under the (a) first snapback state, and (b) second snapback state.
NBL
P-well N-well
STI STI
N+ N+
P-sub P-epi
Drain Source Gate
STI
well P-P+
Body
(a)
Leakage Current (A)
0 5 10 15 20 25 30 35 40
Curent (A)
0.0 0.4 0.8 1.2 1.6 2.0 2.4
2.81e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3
Voltage (V)
GGNMOS W/L= 200/3 µm GGNMOS TLP
(b)
Fig. 4.3 The (a) cross-sectional view, and (b) TLP-measured I-V characteristic, of high-voltage gate-grounded nMOS (GGNMOS) device fabricated in a 0.25-µm 40-V CMOS process.
P-well N-well
Fig. 4.4 The (a) cross-sectional view, and (b) TLP-measured I-V characteristic, of high-voltage silicon controlled rectifier (SCR) device fabricated in a 0.25-µm 40-V CMOS process.
STI N+ STI P+ STI N+ STI P+ STI N+ STI
P-well N-well
NBL N-well
P-sub
Collector Base Emitter Base Collector
(a)
Leakage Current (A)
0 5 10 15 20 25 30 35 40
Curent (A)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.81e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3
Voltage (V) FOD Device W= 200 µm
FOD TLP
(b)
Fig. 4.5 The (a) cross-sectional view, and (b) TLP-measured I-V characteristic, of high-voltage field-oxide (FOD) device fabricated in a 0.25-µm 40-V CMOS process.
NBL
N-well P-well
STI STI
P+ P+
P-sub P-epi
Drain Source Gate
STI
well N-N+
Body
(a)
Leakage Current (A)
0 5 10 15 20 25 30 35 40 45 50 55 60 65
Curent (A)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.81e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3
Voltage (V) GDPMOS W/L= 200/3 µm
TLP GDPMOS
(b)
Fig. 4.6 The (a) cross-sectional view, and (b) TLP-measured I-V characteristic, of high-voltage gate-VDD pMOS (GDPMOS) device fabricated in a 0.25-µm 40-V CMOS process.
DUT
Power Supply
40V
Oscilloscope
Voltage Probe
R1 D1
(10 Ohm)
S1
C1
(200 pF)
Vcharge
Y
Fig. 4.7 The measurement setup for transient latchup (TLU) test.
DUT : GGNMOS Device 40V
0V
~ 7 V Voltage Waveform at Y before transient trigger
after transient trigger with Vcharge= 55 V
Fig. 4.8 The measured voltage waveform on the high-voltage GGNMOS device under TLU test. (Y axis= 10 V/Div., X axis= 100 ns/Div.)
40V
0V
~ 4 V
DUT : SCR Device Voltage Waveform at Y before transient trigger
after transient trigger with Vcharge= 44 V
Fig. 4.9 The measured voltage waveform on the high-voltage SCR device under TLU test.
(Y axis= 10 V/Div., X axis= 100 ns/Div.)
DUT : FOD Device 40V
0V
~ 16 V Voltage Waveform at Y before transient trigger
after transient trigger with Vcharge= 47 V
(a)
DUT : FOD Device 40V
0V
~ 16 V Voltage Waveform at Y before transient trigger
after transient trigger with Vcharge= -10 V
(b)
Fig. 4.10 The measured voltage waveforms on the high-voltage FOD device under TLU test with (a) positive charging voltage, and (b) negative charging voltage. (Y axis= 10 V/Div., X axis= 100 ns/Div.)
FOD TLP
Fig. 4.11 (a) The measurement setup of single high-voltage FOD device and stacked-field-oxide structure under TLP stress. (b) The TLP-measured I-V characteristics of these devices with different device widths. W1 is the channel width of FOD1, and W2 is the channel width of FOD2.
FOD Device Width (µm)
200 300 400 500 600 700 800
It2 (A)
Fig. 4.12 It2 currents of single FOD device and stacked-field-oxide structure as a function of device channel width.
Volatge (V)
Fig. 4.13 The TLP-measured I-V curves of the stacked-field-oxide structure with different substrate-triggered currents.
DUT : Stacked-Field-Oxide Structure 40V
0V
Voltage Waveform at Y before transient trigger
after transient trigger with Vcharge= 80 V
(a)
DUT : Stacked-Field-Oxide Structure 40V
0V
Voltage Waveform at Y before transient trigger
after transient trigger with Vcharge= -50 V
(b)
Fig. 4.14 The measured voltage waveforms on the stacked-field-oxide structure under TLU test with (a) positive charging voltage, and (b) negative charging voltage. (Y axis=
10 V/Div., X axis= 100 ns/Div.)
VDD
VSS
R
C
Mp
Mn
FOD1
FOD2 ESD Detection Circuit
(a)
VDD
VSS
R
C
Mp
Mn
FOD1
FOD2
FOD3 ESD Detection Circuit
(b)
Fig. 4.15 The proposed power-rail ESD clamp circuits in high-voltage CMOS ICs with (a) two cascaded FOD devices, and (b) three cascaded FOD devices.
CHAPTER 5
I/O CELLS WITH EMBEDDED SCR AS POWER-RAIL ESD CLAMP DEVICE IN NANOSCALE CMOS TECHNOLOGY
In nanoscale CMOS technology, how to realize the area-efficient and turn-on-efficient power-rail ESD clamp circuits to protect the ultra-thin gate oxide will be an important challenge to SOC applications with a much larger chip size but a reduced cell pitch for I/O cell. In this chapter, a new ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology is proposed. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell. Such new proposed I/O cells with embedded SCR structure as power-rail ESD clamp device have been successfully verified in a 130-nm CMOS process for SOC applications [54], [55].
5.1 Embedded SCR Structures in I/O Cells
If the holding voltage of the parasitic SCR is greater than the maximum voltage level of circuit operation, the double guard rings surrounding the input (or output) pMOS and nMOS devices in the I/O cells can be removed. To avoid the latchup occurrence in the internal circuits due to the noise triggering at the I/O pad, the additional guard rings should be added between the I/O cells and the core circuits [53]. Thus, the parasitic SCR structure between input (or output) pMOS and nMOS devices can be used as power-rail ESD clamp device in each I/O cell. The layout view and device structures of new proposed I/O cell with embedded SCR structure I are shown in Figs. 5.1(a) and 5.1(b), respectively. Keeping the single guard
inserting the extra p+ diffusion in n-well and the extra n+ diffusion in p-well, respectively. To enhance the turn-on speed of embedded SCR structure, the p+ diffusion inserted half in n-well and half in p-well is connected out as substrate-triggered node. When a trigger current is applied into this trigger node, SCR will be triggered into its latching state quickly through the positive feedback regeneration mechanism [81]. The substrate-triggered technique can be realized by the RC-based ESD detection circuit [82]. With RC-based ESD detection circuit, the embedded SCR structure is kept off during the normal circuit operating condition, but it can be quickly triggered on during the ESD stress condition.
The ESD current discharging paths through the I/O cell with embedded SCR structure I under PS-mode, PD-mode, NS-mode, and ND-mode ESD stresses are shown in Figs. 5.2(a) ~ 5.2(d), respectively. The ESD current at the I/O pad under PS-mode ESD stress can be discharged through two discharging paths (path A and path B), as the dashed lines shown in Fig. 5.2(a). The first discharging path (path A) is that the ESD current is discharged through the parasitic diode of pMOS (Mp) to VDD, and then through the embedded SCR structure from the VDD power line to the grounded VSS power line. The second discharging path (path B) is that the ESD current is directly discharged through the parasitic SCR structure from the I/O pad to the grounded VSS power line. Because the ESD current will be discharged through parasitic forward-diode path to VDD first, the ESD detection circuit can detect such ESD pulse to provide the substrate-triggered current to raise up the local substrate potential. The embedded SCR structure and the parasitic SCR structure from drain of pMOS to the grounded n+ in p-well can be quickly triggered on to discharge the ESD current by such substrate-triggered current. The major ESD current will be discharged through the path with lower clamping voltage and lower turn-on resistance. The ESD current at the I/O pad under PD-mode ESD stress can be discharged through the parasitic diode of pMOS (Mp) to the grounded VDD power line, as the dashed lines shown in Fig. 5.2(b). The negative ESD current at the I/O pad under NS-mode ESD stress can be discharged through the parasitic diode of nMOS (Mn) to the grounded VSS power line, as the dashed lines shown in Fig.
5.2(c). The negative ESD current at the I/O pad under ND-mode ESD stress can be discharged through two discharging paths (path C and path D), as the dashed lines shown in Fig. 5.2(d). The first discharging path (path C) is that the negative ESD current is discharged through the parasitic diode of nMOS (Mn) to VSS, and then through the embedded SCR structure from the VSS power line to the grounded VDD power line. The second discharging path (path D) is that the negative ESD current is directly discharged through the parasitic
SCR structure from the I/O pad to the grounded VDD power line. Because the negative ESD current will be discharged through parasitic forward-diode path to VSS first, the ESD detection circuit can detect such ESD pulse to provide the substrate-triggered current to raise up the local substrate potential. The embedded SCR structure and the parasitic SCR structure from the p+ connected to VDD in n-well to the drain of nMOS can be quickly triggered on to discharge the ESD current by such substrate-triggered current. With the two discharging paths, the ESD robustness of the I/O pad under PS-mode and ND-mode ESD stresses can be further improved. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed I/O cell with embedded SCR structure I.
The layout area of the I/O cell can be further reduced by the new embedded SCR structure II. The layout view and device structures of new proposed I/O cell with embedded SCR structure II are shown in Figs. 5.3(a) and 5.3(b), respectively. Without the double guard rings, the anode and cathode of embedded SCR structure II are directly formed by the source of input (or output) pMOS and the source of nMOS, respectively. The poly gate in the layout view has a close-loop ring to increase the anode and cathode areas of embedded SCR structure II. The ESD current discharging paths of the I/O cell with embedded SCR structure II under four modes ESD stresses are the same with that of I/O cell with embedded SCR structure I. Especially, under the PS-mode ESD stress, the parasitic SCR (path B) from the drain of pMOS to the source of nMOS can be triggered on to discharge ESD current. Under the ND-mode ESD stress, the parasitic SCR (path D) from the source of pMOS to the drain of nMOS provides the second ESD discharging path. It is important to note that the second discharging path for I/O cell with embedded SCR structure II under PS-mode ESD stress (path B) or under ND-mode ESD stress (path D) becomes more efficient due to the smaller anode-to-cathode spacing of the parasitic SCR structure. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed I/O cell with embedded SCR structure II.
The new proposed whole-chip ESD protection scheme with embedded SCR structure as power-rail ESD clamp device in each I/O cell is shown in Fig. 5.4. Several I/O cells can share one ESD detection circuit to reduce the layout area for high-pin-count applications. With the embedded SCR structure in each I/O cell, the whole-chip ESD protection efficiency is not degraded by the different pin locations in the chip. This will be more valuable for applications in the SOC chip with hundreds of I/O pins.
5.2 Experimental Results
The testchips with the traditional I/O cells and the new proposed I/O cells have been fabricated in a 130-nm salicided CMOS process. The input ESD protection devices are realized by the gate-connected-to-source pMOS (GDPMOS) and gate-grounded nMOS (GGNMOS) with the device dimensions (W/L) of 240/0.18 and 180/0.18 (µm/µm), respectively. The output ESD protection devices are realized by the output buffer of pMOS and nMOS with the same device dimensions as those of the input cell. The layout parameters of input ESD protection devices and output buffers are drawn according to the foundry’s ESD rules with or without silicide blocking for comparison. In the new proposed I/O cells, the embedded SCR structures I and II are fully silicided with the SCR device widths of 49.5 and 45.5µm, respectively. The spacing from anode to cathode of the embedded SCR structure is kept at 2.35µm. The total layout area of the whole I/O cell with embedded SCR structure I is only 60µm × 50µm, and that with embedded SCR structure II is only 50µm × 50µm. The ESD detection circuit including R, C, and inverter is realized with R= 60kΩ, C= 3pF, pMOS dimension W/L= 40/0.18 (µm/µm), and nMOS dimension W/L= 8/0.18 (µm/µm). One set of delay-based R and C in the ESD detection circuit can be shared for all I/O cells, which are powered with the same power domain. Such R and C can be implemented in the area of VDD or VSS cells, which provide the power for I/O cells.
5.2.1 DC I-V Characteristics
To avoid the latchup issue, the holding voltage of ESD protection circuit with SCR device must be designed greater than the maximum voltage level of VDD. The dc I-V characteristics of embedded SCR structures I and II in the I/O cells are measured (using Tek370 curve tracer) by applying a voltage sweep on the VDD pin under the bias condition of 0-V VSS but I/O pad is floating. The measured dc I-V characteristics of embedded SCR structures I and II under different temperatures are shown in Figs. 5.5(a) and 5.5(b), respectively. The dependence of holding voltage of embedded SCR structures under different temperatures is summarized in Fig. 5.6. From the measured results, the holding voltage of embedded SCR structures slightly reduces when the temperature is increased, because the current gain (β) of the parasitic bipolar transistor in the SCR device is increased with the increase of temperature. With smaller equivalent well resistance, the holding voltage of embedded SCR structure I is larger
and II at temperature of 125oC are 1.54V and 1.27V, respectively, which are both greater than VDD of 1.2V. The measured results have verified that the embedded SCR structures can be safely applied in 1.2-V CMOS ICs without latchup issue. Especially, the embedded SCR I has a high switching current of greater than 200mA in Fig. 5.5(a), which is suitable for application in the noisy environment to avoid the accidentally triggering.
The measured dc I-V characteristics of embedded SCR structures I and II in the I/O cells under different substrate-triggered currents (Itrig) are shown in Figs. 5.7(a) and 5.7(b), respectively. As shown in Fig. 5.7, the trigger voltage of the embedded SCR structure I without the substrate-triggered current is ~8.5V (by p+ trigger node/n-well junction breakdown), and that of the embedded SCR structure II is ~8V. The switching current and trigger voltage of the embedded SCR structure are decreased while the substrate-triggered current is increased. ESD protection devices with low trigger voltage can be turned on more quickly to discharge ESD current to provide more effective protection for internal circuits. To provide effective ESD protection to the ultra-thin gate oxide in 130-nm CMOS process, the substrate-triggered current of 12mA for embedded SCR structure I and substrate-triggered current of 6mA for embedded SCR structure II are the design suggestion.
As the discussions in section 5.1, one parasitic SCR structure (path B) between I/O pad and VSS power line can be triggered on to discharge ESD current for I/O pad under PS-mode ESD stress, and another parasitic SCR structure (path D) between I/O pad and VDD power line can be triggered on to discharge ESD current for I/O pad under ND-mode ESD stress.
The dc I-V characteristics of these parasitic SCR structures for I/O cell with embedded SCR structure II are measured to verify their effectiveness. The dc I-V characteristics of parasitic SCR structure (path B) between I/O pad and VSS power line are measured by applying a voltage sweep on the I/O pad under the bias condition of 0-V VSS but VDD is floating similar to PS-mode. The measured dc I-V characteristics of parasitic SCR structure (path B) between I/O pad and VSS power line under different substrate-triggered currents are shown in Fig. 5.8(a). In addition, the dc I-V characteristics of parasitic SCR structure (path D) between I/O pad and VDD power line are measured by applying a negative voltage sweep on the I/O pad under the bias condition of 0-V VDD but VSS is floating similar to ND-mode. The measured dc I-V characteristics of parasitic SCR structure (path D) between I/O pad and VDD power line under different substrate-triggered currents are shown in Fig. 5.8(b). From the measured results, the holding voltage of parasitic SCR structure (path B) between I/O pad and VSS power line at temperature of 25oC is 1.84V, and that of parasitic SCR structure (path
D) between I/O pad and VDD power line is 1.6V. The trigger voltage of parasitic SCR structure between I/O pad and VSS power line without the substrate-triggered current is
~3.5V (by n+/p-well of nMOS junction breakdown), and that of parasitic SCR structure between I/O pad and VDD power line is ~5.5V (by p+/n-well of pMOS junction breakdown).
The trigger voltage of these parasitic SCR structures can be effectively decreased while the substrate-triggered current is increased. Although the trigger voltage of these parasitic SCR structures without the substrate-triggered current is lower than that of embedded SCR structure, both SCR structures can be triggered on quickly to discharge ESD current with the appropriate substrate-triggered current generated from the ESD detection circuit.
5.2.2 TLP I-V Characteristics
To investigate the device behavior during high ESD current stress, transmission line pulse (TLP) generator with a pulse width of 100ns and a rise time of ~10ns is used to measure the second breakdown current (It2) of the device [75]. The TLP-measured I-V characteristics of the I/O cells with embedded SCR structures under positive VDD-to-VSS ESD stress with or without ESD detection circuit are shown in Fig. 5.9(a). The enlarged view around the switching point for I/O cells with ESD detection circuit is shown in Fig. 5.9(b). From the measured results, the trigger voltages of embedded SCR structures I and II without ESD detection circuit are 10.5V and 8.8V, respectively. However, the trigger voltages of embedded SCR structures I and II can be reduced to only 2.7V and 1.74V, respectively, by the ESD detection circuit without involving the avalanche junction breakdown mechanism. Therefore, the trigger voltage of embedded SCR structure can be significantly reduced by substrate-triggered technique to ensure effective ESD protection. The It2 per micron of embedded SCR structure is as high as ~100mA/µm, without using the silicide-blocking process modification.
The TLP-measured I-V curves of I/O cells with or without embedded SCR structure under PS-mode ESD stress are compared in Fig. 5.10. Without the embedded SCR structure, the ESD current at the input pad under PS-mode ESD stress is discharged through the
The TLP-measured I-V curves of I/O cells with or without embedded SCR structure under PS-mode ESD stress are compared in Fig. 5.10. Without the embedded SCR structure, the ESD current at the input pad under PS-mode ESD stress is discharged through the