CHAPTER 6 CONCLUSIONS AND FUTURE WORKS
6.2 Future Works
In mixed-voltage I/O interfaces, the effective ESD protection design has been proposed and verified in this thesis. But, for some mixed-voltage circuit applications, the power supply voltage may exceed the ordinary VDD of the process to drive a high-voltage output signal.
Therefore, it is required to design the high-voltage-tolerant power-rail ESD clamp circuit with
low-voltage devices but without suffering the gate-oxide reliability issue. In the high-voltage-tolerant power-rail ESD clamp circuit, the standby leakage current between the power rails is an important concern, especially when the IC is operating at high-temperature environment. In high-voltage CMOS technology, the total holding voltage of the stacked-device structure can be designed higher than the supply voltage to avoid the latchup or latchup-like issues in high-voltage CMOS ICs. But, the layout area of the stacked-device structure will increase as compared to that of the single device, especially for high ESD robustness requirement. The design of new device with the characteristics of both high holding voltage and high ESD robustness from the structure design or process modification will be a useful solution. In nanoscale CMOS technology, the ESD protection design for the charged-device model (CDM) ESD event will be another challenge to protect the ultra-thin gate oxide, especially for the SOC applications with a large chip area. Such ESD topics will be the continual future works for research.
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簡 歷
姓 名：林昆賢
性 別：男
出生日期：民國62年6月25日
出 生 地：台灣省屏東縣
住 址：屏東縣萬巒鄉成德村恭寬路2號
學 歷：
國立交通大學電子工程系畢業 (81年9月~85年6月)
國立交通大學電子研究所碩士班畢業 (85年9月~87年6月)
國立交通大學電子研究所博士班 (90年9月入學)
論文名稱：適用於高低壓共容輸入輸出介面之積體電路靜電放電防護設 計
ESD Protection Designs for Mixed-Voltage I/O Interfaces in CMOS Integrated Circuits
PUBLICATION LIST
(A) Referred Journal Papers:
[1] Ming-Dou Ker and Kun-Hsien Lin, “Design on ESD protection scheme for IC with power-down-mode operation,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1378-1382, Aug. 2004.
[2] Ming-Dou Ker and Kun-Hsien Lin, “Double snapback characteristics in high-voltage nMOFETs and the impact to on-chip ESD protection design,” IEEE Electron Device Letters, vol. 25, no. 9, pp. 640-642, Sept. 2004.
[3] Ming-Dou Ker, Kun-Hsien Lin, and Chien-Hui Chuang, “On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process,” IEEE Trans. on Electron Devices, vol. 51, no. 10, pp. 1628-1635, Oct. 2004.
[4] Kun-Hsien Lin and Ming-Dou Ker, “Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board,” Journal of Microelectronics Reliability, in press, 2005.
[5] Ming-Dou Ker, Kun-Hsien Lin, and Che-Hao Chuang, “MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process,” IEICE Trans. on Electronics, in press, 2005.
[6] Ming-Dou Ker and Kun-Hsien Lin, “The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs,” revised by IEEE Journal of Solid-State Circuits.
[7] Ming-Dou Ker and Kun-Hsien Lin, “ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology,” submitted to IEEE Journal of Solid-State Circuits.
[8] Ming-Dou Ker and Kun-Hsien Lin, “Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations,” submitted to IEEE Trans. on Circuits and Systems I.
(B) International Conference Papers:
[1] Ming-Dou Ker, Kun-Hsien Lin, and Che-Hao Chuang, “MOS-bounded diodes for on-chip ESD protection in a 0.15-µm shallow-trench-isolation salicided CMOS
process,” in Proc. of International Symposium on VLSI Technology, Systems, and Applications, 2003, pp. 84-87.
[2] Ming-Dou Ker and Kun-Hsien Lin, “ESD protection design for IC with power-down-mode operation,” in Proc. of IEEE International Symposium on Circuits and Systems, 2004, pp. 717-720.
[3] Kun-Hsien Lin and Ming-Dou Ker, “Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs,” in Proc. of EOS/ESD Symposium, 2004, pp.
265-272.
[4] Kun-Hsien Lin and Ming-Dou Ker, “ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure,” in Proc. of IEEE International Symposium on Circuits and Systems, 2005, in press.
(C) Local Conference Papers:
[1] Kun-Hsien Lin and Ming-Dou Ker, “Whole-chip ESD protection design for IC with power-down application,” in Proc. of Taiwan ESD Conference, 2003, pp. 142-147.
[2] Kun-Hsien Lin and Ming-Dou Ker, “Latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs ,” in Proc. of Taiwan ESD Conference, 2004, pp. 25-30.
(D) Patents:
[1] 柯明道、林昆賢, “靜電放電防護電路,” 中華民國發明專利, Nov. 2004. (專利證 書號 # 224391)。
[2] 柯明道、林昆賢, “可避免鎖住效應之高壓積體電路電源間靜電放電箝制電路,”
中華民國發明專利，申請中。
[3] Ming-Dou Ker and Kun-Hsien Lin, “ESD protection circuit for IC with power-down-mode operation,” USA patent pending.
[4] Ming-Dou Ker and Kun-Hsien Lin, and Geeng-Lih Lin, “Electrostatic discharge protection device,” USA patent pending.
[5] Ming-Dou Ker and Kun-Hsien Lin, “A silicon controlled rectifier for the electrostatic discharge protection,” ROC and USA patent pending.
[6] Ming-Dou Ker and Kun-Hsien Lin, “ESD protection design against charge-device model ESD events,” ROC and USA patent pending.