Thesis Organization - 適用於高低壓共容輸入輸出介面之積體電路靜電放電防護設計

CHAPTER 1 INTRODUCTION

1.3 Thesis Organization

To overcome the ESD design constraints in mixed-voltage I/O interfaces, power-down-mode application, high-voltage CMOS process, and nanoscale CMOS technology, the novel on-chip ESD protection circuits are developed and verified in this thesis.

This thesis contains six chapters. Chapter 1 presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. To improve ESD level of the mixed-voltage I/O circuits, the ESD protection design without increasing the process complexity is strongly requested by the mixed-voltage I/O circuits in consumer IC products.

Such ESD protection design in the mixed-voltage I/O circuits still meets the gate-oxide reliability constraints, and needs to prevent the undesired leakage current paths during normal circuit operating condition. Under ESD stress condition, the ESD protection circuit should be quickly triggered on to discharge ESD current.

In chapter 2, the substrate-triggered stacked-nMOS device, which combines the substrate-triggered technique with the stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The proposed ESD protection circuit with the

substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5V/3.3V tolerant mixed-voltage I/O circuit in a 0.25-µm salicided CMOS process. The HBM ESD level of the mixed-voltage I/O buffer can be improved from the original 3.4kV up to 5.6kV by the substrate-triggered circuit. By using this substrate-triggered design, the ESD robustness of mixed-voltage I/O circuits can be effectively improved without occupying extra silicon area to realize the additional stand-alone ESD protection device into the I/O cells.

In chapter 3, three new ESD protection designs for CMOS IC with power-down-mode operation are proposed. By using the additional ESD bus and diodes, the ESD protection design can block the leakage current from I/O pin to VDD and avoid the malfunction during power-down-mode operating condition. During normal circuit operating condition, the ESD protection design has no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and ESD bus. Experimental results have verified that the HBM ESD level of the new proposed designs can be greater than 7.5kV in a 0.35-µm silicided CMOS process. Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition.

In chapter 4, the double snapback characteristic in the high-voltage nMOSFETs has been found and analyzed. Furthermore, the holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup or latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-µm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40V.

In chapter 5, a new ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in a 130-nm CMOS process is proposed. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output)

pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the HBM ESD level of this new proposed I/O cells can be greater than 5kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell.

Finally, the main results of this thesis are summarized in chapter 6. Some suggestions for the future works are also addressed in this chapter.

VDD

Fig. 1.1 The four pin-combination modes for ESD test on an IC product: (a) positive-to-VSS (PS-mode), (b) negative-to-VSS (NS-mode), (c) positive-to-VDD (PD-mode), and (d) negative-to-VDD (ND-mode).

Internal

Fig. 1.2 Typical on-chip ESD protection circuits in a CMOS IC.

I/O

Fig. 1.3 Typical circuit diagrams for (a) the traditional CMOS I/O buffer, and (b) the mixed-voltage I/O circuits with the stacked-nMOS and the N-well self-biased pMOS.

PadI/O VDD

VSS

Pre-Driver

Power-Rail ESD Clamp Circuit V^ESD

GND I^ESD I^ESD

(a)

I/O Pad VDD

VSS

Pre- Driv er

VDD

N-well Self-Biased

Circuit Gate

Tracking Circuit

Stacked NMOS

Power-Rail ESD Clamp Circuit

GND

V

ESD

I

^ESD

(b)

Fig. 1.4 The ESD current paths of (a) the traditional I/O pad with power-rail ESD clamp circuit, and (b) the mixed-voltage I/O pad with power-rail ESD clamp circuit, under the positive-to-VSS (PS-mode) ESD stress. The ESD current paths are indicated by the dashed lines.

VDD1 VDD2

VSS

CHIP1 CHIP2

O/P I/P

System

Internal Circuits Internal

Circuits

Mp1 Mp2

Mn1 Mn2

Fig. 1.5 An example to show the power-down-mode operation issue on a system with two chips, which are biased with separated VDD1 and VDD2 power supplies.

Output PAD

Level-shifter Circuits

Input Control Circuits

VDD_HV

VSS

VDD_LV

Input R PAD

Power-Rail ESD Clamp Circuit VESD

I_ESD

R D1

Fig. 1.6 The typical ESD protection scheme for LCD driver ICs.

(a)

VD D

40V

0V Time (ns)

due to the discharge of ESD energy

t

ESD

(b)

Fig. 1.7 (a) The system-level EMC/ESD test on LCD panel of notebook by an ESD gun. (b) The transient overshooting/ undershooting voltage waveform on the VDD pin of the driver ICs during system-level EMC/ESD test.

N+ double ring Poly gate

Poly gate P+ double ring

PMOS (Mp)

NMOS (Mn) N+ single ring

P+ single ring

(a)

P-sub N-well

P+ P+ N+ N+

P-well

P+ N+

VDD VSS

N-well P-well

N+

P+

VDD

Mp VSS Mn

P+

VSS

N+

VDD

Input/Output Pad

(b)

Fig. 1.8 (a) Layout view and (b) device structures of the traditional I/O cell with double guard rings inserted between input (or output) pMOS and nMOS devices.

Internal

Fig. 1.9 (a) ESD protection design with substrate-triggered lateral n-p-n BJT device to protect the mixed-voltage I/O circuits. (b) Cross-sectional view of the lateral n-p-n BJT device in a thin-epi CMOS process.

SNTSCR

Fig. 1.10 (a) ESD protection circuit with the SNTSCR device to protect the mixed-voltage I/O circuits. (b) Realizations of the SNTSCR device and the ESD detection circuit with the gate-coupling technique to trigger on the SNTSCR device.

Internal

Fig. 1.11 ESD protection design with the diode string connected between the I/O pad and VDD power line to protect the mixed-voltage I/O circuits. An additional snubber diode (SD) is used to reduce the leakage current of the diode string due to the Darlington amplification.

Pad I/O

Fig. 1.12 ESD protection design with gated p-n-p BJT as the ESD clamp device connected between I/O pad and VDD to protect the mixed-voltage I/O circuits.

Internal

Circuit s Internal Circuits

Stacked-NMOS Pull-up PMOS

Gate Tracking

Circuit

N-Well Self-Biased

Circuit

VSS

VDD Pad

I/O

VDD

Second Power-Rail ESD Clamp Circuit (High-Voltage-Tolerant)

ESD Bus

First Power-Rail ESD Clamp Circuit

Fig. 1.13 The ESD protection network with the additional ESD bus line for the mixed-voltage I/O circuits. One power-rail ESD clamp circuit is connected between VDD power line and VSS power line. A second power-rail ESD clamp circuit is connected between ESD bus line and VSS power line.

VSS

Fig. 1.14 ESD protection design with low-voltage-triggered p-n-p (LVTPNP) device for the I/O interfaces with input voltage level higher than VDD or lower than VSS.

VSS

Fig. 1.15 High-voltage-tolerant ESD protection design with the forward-biased diode in series with one stacked nMOS for analog ESD protection to reduce the input parasitic capacitance.

CHAPTER 2 ESD PROTECTION DESIGN FOR MIXED-VOLTAGE I/O CIRCUITS

In this chapter, a new ESD protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs.

The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The substrate-triggered circuit for providing the trigger current should be designed to avoid electrical overstress on the gate oxide and to prevent the undesired leakage current paths during normal circuit operating condition. During ESD stress condition, the substrate-triggered circuit should generate large enough current to effectively improve the turn-on efficiency of parasitic n-p-n BJT in stacked-nMOS device. The substrate-triggered circuit should meet above constraints for providing effective ESD protection to the mixed-voltage I/O interfaces. By using this substrate-triggered design, the gates of stacked-nMOS in the mixed-voltage I/O circuits can be fully controlled by the pre-driver of I/O circuits without conflict to the ESD protection circuits. The main ESD discharge device is the parasitic n-p-n BJT in the stacked-nMOS device. Therefore, the ESD robustness of mixed-voltage I/O circuits can be effectively improved without occupying extra silicon area to realize the additional stand-alone ESD protection device into the I/O cells. Without using the thick gate oxide, this new design has been fabricated and verified for 2.5V/3.3V tolerant mixed-voltage I/O circuit in a 0.25-µm salicided CMOS process [31].

2.1 Stacked-NMOS Device

The finger-type layout pattern and the corresponding cross-sectional view of stacked-nMOS device in mixed-voltage I/O circuits are shown in Figs. 2.1(a) and 2.1(b), respectively. The stacked-nMOS device can be used as both of the pull-down device and ESD protection device in the mixed-voltage I/O circuits. The stacked-nMOS structure includes a

first transistor (top nMOS), having a drain connected to an I/O pad, and a gate (VG1) connected to the VDD power supply. A second transistor (bottom nMOS) is merged into the same active area of the first transistor, having a gate (VG2) connected to the pre-driver of the mixed-voltage I/O circuits. The source of the top nMOS and the drain of the bottom nMOS are constructed together by sharing the common n+ diffusion region.

Under the PS-mode ESD stress condition, the stacked-nMOS is operated in snapback breakdown, with the bipolar effect taking place between the drain of the top nMOS and the source of the bottom nMOS. These two diffusions are acted as bipolar emitter and collector, respectively. Their spacing determines the base width and turn-on efficiency of the lateral bipolar transistor. The snapback mechanism of stacked-nMOS for conducting large amount of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar transistor. The hole current (Isub) generated from drain avalanche breakdown, drifting through the effective substrate resistance (Rsub) to ground, may elevate the substrate potential (Vsub) of the emitter-base junction in the lateral bipolar transistor. The voltage level, which the local substrate potential is elevated, depends on the relative proximity to the avalanching junction. When the emitter-base junction of bipolar transistor begins to weakly forward bias due to the increase of local substrate potential, additional electron current through the bipolar device is acted as “seed current” to drive a significant increase in the multiplication rate and avalanche current generation at the collector-base junction of the lateral bipolar transistor. Therefore, a “snapback” is seen, and the lateral bipolar transistor enters strong bipolar conduction to discharge ESD current.

The dependences of HBM ESD level on the device channel width and poly-to-poly spacing (common n+ diffusion spacing) of stacked-nMOS device in a 0.25-µm CMOS process are shown in Fig. 2.2. In Fig. 2.2(a), the HBM ESD level of the stacked-nMOS device is increased while the device channel width is increased. Moreover, the stacked-nMOS device with silicide-blocking process can sustain higher ESD level than that with fully silicided process. The non-uniform turn-on issue of the parasitic n-p-n BJT in stacked-nMOS device can be improved by the silicide-blocking process. In Fig. 2.2(b), the HBM ESD level of stacked-nMOS device with fully silicided process is decreased obviously while the poly-to-poly spacing is increased. However, the HBM ESD level of stacked-nMOS device with silicide-blocking process is only decreased slightly. The turn-on efficiency and performance of the parasitic n-p-n BJT in stacked-nMOS device can be improved by reducing the poly-to-poly spacing. Therefore, the ESD robustness of stacked-nMOS device can be

somewhat improved by layout optimization.

2.2 Stacked-NMOS with Substrate-Triggered Technique

2.2.1 Substrate-Triggered Stacked-NMOS Device

The snapback operation of stacked-nMOS device depends on the substrate current (Isub), which is created at the reverse-biased drain/substrate junction, to forward bias the source/substrate junction. Hence, the substrate resistance (Rsub) and substrate current (Isub) are the important design parameters for ESD protection [73], [74]. However, the substrate-triggered technique [56]-[58] can be used to generate the substrate current. With the substrate-triggered current, the trigger voltage of the stacked-nMOS device in mixed-voltage I/O circuits can be reduced for more effective ESD protection. In this work, the substrate-triggered stacked-nMOS device, which combines the substrate-triggered technique with the stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs.

The finger-type layout pattern and the corresponding cross-sectional view of the new proposed substrate-triggered stacked-nMOS device are shown in Fig. 2.3(a) and Fig. 2.3(b), respectively. As shown in Fig. 2.3, an additional p+ diffusion is inserted into the center drain region of stacked-nMOS device as the substrate-triggered point. The trigger current (Itrig) is provided by the substrate-triggered circuit. An n-well structure is further diffused under the source region, which is also surrounding the whole device, to form a higher equivalent substrate resistance for improving turn-on efficiency of the parasitic lateral bipolar transistor in the stacked-nMOS device.

2.2.2 ESD Protection Circuit

The ESD protection design, which includes the substrate-triggered stacked-nMOS device and the substrate-triggered circuit for the mixed-voltage I/O circuits, is shown in Fig. 2.4. The substrate-triggered circuit is composed of the diode string, a pMOS Mp1, and an nMOS Mn1, to provide the substrate current for triggering on the parasitic lateral bipolar transistor in the stacked-nMOS device while the ESD voltage is applied on the I/O pad. The anode of the diode string in the substrate-triggered circuit and the collector of the parasitic bipolar

string is connected to the source of Mp1. The emitter (the base) of the lateral bipolar transistor is connected to the VSS power line (the drain of Mp1). The nMOS Mn1 is connected between the base of the lateral bipolar transistor and the VSS power line. The gates of Mp1 and Mn1 are connected together to the VDD power line through a resistor. The resistor is realized by an n+ diffusion with a parasitic n+/p-sub diode to avoid the antenna effect during the CMOS process fabrication. The diode string including in the substrate-triggered circuit is composed of individual diodes formed by using P+ diffusion in the separated n-well structure. The total voltage drop across the diode string can be expressed as [64]:

Vstring = total voltage drop across the m diodes,

m= the number of diodes in the diode string, n= ideality factor, and

β= the beta gain of the parasitic vertical pnp bipolar transistor in the diode structure.

During the ESD stress condition, the Mp1 is used in conjunction with the diode string to provide the substrate current to trigger the parasitic lateral bipolar transistor in the stacked-nMOS device. Once the lateral bipolar transistor in the stacked-nMOS device has been turned on, the ESD current is discharged from the I/O pad to VSS.

2.2.3 Operating Principles

Fig. 2.5 shows the cross-sectional view of the substrate-triggered stacked-nMOS device with the substrate-triggered circuit for protecting mixed-voltage I/O circuits. In the normal circuit operating condition, the substrate-triggered circuit should remain in a non-conductive state, so that it does not interfere with the voltage levels on the I/O pad. For the 2.5V/3.3V mixed-voltage IC application, 3.3V tolerance was desired for normal circuit operation with a 2.5-V VDD supply in the chip. The turn-on voltage of the substrate-triggered circuit roughly equals to Vpad ≧ V^string(I)+|Vtp|+VDD, where the Vtp is the threshold voltage of the pMOS Mp1. The turn-on voltage can be adjusted by varying the numbers of the diodes in the diode string. To satisfy the requirement in the 2.5V/3.3V mixed-voltage application, the number of

the diodes in the diode string should be adjusted to let the turn-on voltage greater than 3.3V.

When the I/O pad is applied with a high input voltage of 3.3V, Mp1 is still kept off, and the local substrate of the stacked-nMOS is biased at VSS by the turned-on Mn1. With the diode string to block the 3.3V input voltage on the I/O pad, the Mp1 with thin gate oxide has no gate-oxide reliability issue during the normal circuit operating condition.

The choice of a particular diode string is also determined by the specified pin leakage current at a given temperature. If a lower input leakage is desired, the numbers of the diodes in the diode string should be increased. Since the diode string is not the main ESD current discharge path, its perimeter can be adjusted with less impact on ESD performance. The leakage current problem of the diode string comes from the parasitic vertical pnp bipolar transistor of each diode formed by the P+ diffusion in an n-well. The Mp1 in conjunction with a diode string is used to reduce the leakage current at the I/O pad in the normal operating condition. Moreover, the Mn1 with its gate biased at VDD is always turned on to bypass any leakage current, which may trigger on the lateral npn bipolar transistor in the normal circuit operating condition.

Under the PS-mode ESD stress condition, the gate of the Mp1 has an initial voltage level of ~0V, while the VSS pin is grounded but the VDD pin is floating. The substrate-triggered circuit will provide the trigger current flowing through the diode string and the Mp1 into the p-substrate, when Vpad ≧ Vstring(I)+ |Vtp|. For a given Rsub, the substrate-triggered circuit must supply an enough trigger current (Itrig) to raise up the local substrate potential, so that VBE (= Isub x Rsub) > 0.6V for triggering on the parasitic lateral n-p-n bipolar transistor in the stacked-nMOS device. Once the lateral bipolar transistor is turned on, the ESD current is discharged from the I/O pad through the lateral bipolar transistor to the grounded VSS. The trigger current provided by the substrate-triggered circuit is determined by the diode string and the size of Mp1. With an appropriate trigger current, the substrate potential is raised up to trigger on the lateral bipolar transistor and to reduce the trigger voltage of the ESD protection circuit. Therefore, ESD robustness of the mixed-voltage I/O circuits with the stacked-nMOS device can be effectively improved by this new proposed substrate-triggered design. It is important to note that the device size of Mp1 should be large enough than that of Mn1 to

在文檔中適用於高低壓共容輸入輸出介面之積體電路靜電放電防護設計 (頁 32-0)