DC I-V Characteristics

To avoid the latchup issue, the holding voltage of ESD protection circuit with SCR device must be designed greater than the maximum voltage level of VDD. The dc I-V characteristics of embedded SCR structures I and II in the I/O cells are measured (using Tek370 curve tracer) by applying a voltage sweep on the VDD pin under the bias condition of 0-V VSS but I/O pad is floating. The measured dc I-V characteristics of embedded SCR structures I and II under different temperatures are shown in Figs. 5.5(a) and 5.5(b), respectively. The dependence of holding voltage of embedded SCR structures under different temperatures is summarized in Fig. 5.6. From the measured results, the holding voltage of embedded SCR structures slightly reduces when the temperature is increased, because the current gain (β) of the parasitic bipolar transistor in the SCR device is increased with the increase of temperature. With smaller equivalent well resistance, the holding voltage of embedded SCR structure I is larger

and II at temperature of 125^oC are 1.54V and 1.27V, respectively, which are both greater than VDD of 1.2V. The measured results have verified that the embedded SCR structures can be safely applied in 1.2-V CMOS ICs without latchup issue. Especially, the embedded SCR I has a high switching current of greater than 200mA in Fig. 5.5(a), which is suitable for application in the noisy environment to avoid the accidentally triggering.

The measured dc I-V characteristics of embedded SCR structures I and II in the I/O cells under different substrate-triggered currents (Itrig) are shown in Figs. 5.7(a) and 5.7(b), respectively. As shown in Fig. 5.7, the trigger voltage of the embedded SCR structure I without the substrate-triggered current is ~8.5V (by p+ trigger node/n-well junction breakdown), and that of the embedded SCR structure II is ~8V. The switching current and trigger voltage of the embedded SCR structure are decreased while the substrate-triggered current is increased. ESD protection devices with low trigger voltage can be turned on more quickly to discharge ESD current to provide more effective protection for internal circuits. To provide effective ESD protection to the ultra-thin gate oxide in 130-nm CMOS process, the substrate-triggered current of 12mA for embedded SCR structure I and substrate-triggered current of 6mA for embedded SCR structure II are the design suggestion.

As the discussions in section 5.1, one parasitic SCR structure (path B) between I/O pad and VSS power line can be triggered on to discharge ESD current for I/O pad under PS-mode ESD stress, and another parasitic SCR structure (path D) between I/O pad and VDD power line can be triggered on to discharge ESD current for I/O pad under ND-mode ESD stress.

The dc I-V characteristics of these parasitic SCR structures for I/O cell with embedded SCR structure II are measured to verify their effectiveness. The dc I-V characteristics of parasitic SCR structure (path B) between I/O pad and VSS power line are measured by applying a voltage sweep on the I/O pad under the bias condition of 0-V VSS but VDD is floating similar to PS-mode. The measured dc I-V characteristics of parasitic SCR structure (path B) between I/O pad and VSS power line under different substrate-triggered currents are shown in Fig. 5.8(a). In addition, the dc I-V characteristics of parasitic SCR structure (path D) between I/O pad and VDD power line are measured by applying a negative voltage sweep on the I/O pad under the bias condition of 0-V VDD but VSS is floating similar to ND-mode. The measured dc I-V characteristics of parasitic SCR structure (path D) between I/O pad and VDD power line under different substrate-triggered currents are shown in Fig. 5.8(b). From the measured results, the holding voltage of parasitic SCR structure (path B) between I/O pad and VSS power line at temperature of 25^oC is 1.84V, and that of parasitic SCR structure (path

D) between I/O pad and VDD power line is 1.6V. The trigger voltage of parasitic SCR structure between I/O pad and VSS power line without the substrate-triggered current is

~3.5V (by n+/p-well of nMOS junction breakdown), and that of parasitic SCR structure between I/O pad and VDD power line is ~5.5V (by p+/n-well of pMOS junction breakdown).

The trigger voltage of these parasitic SCR structures can be effectively decreased while the substrate-triggered current is increased. Although the trigger voltage of these parasitic SCR structures without the substrate-triggered current is lower than that of embedded SCR structure, both SCR structures can be triggered on quickly to discharge ESD current with the appropriate substrate-triggered current generated from the ESD detection circuit.

5.2.2 TLP I-V Characteristics

To investigate the device behavior during high ESD current stress, transmission line pulse (TLP) generator with a pulse width of 100ns and a rise time of ~10ns is used to measure the second breakdown current (It2) of the device [75]. The TLP-measured I-V characteristics of the I/O cells with embedded SCR structures under positive VDD-to-VSS ESD stress with or without ESD detection circuit are shown in Fig. 5.9(a). The enlarged view around the switching point for I/O cells with ESD detection circuit is shown in Fig. 5.9(b). From the measured results, the trigger voltages of embedded SCR structures I and II without ESD detection circuit are 10.5V and 8.8V, respectively. However, the trigger voltages of embedded SCR structures I and II can be reduced to only 2.7V and 1.74V, respectively, by the ESD detection circuit without involving the avalanche junction breakdown mechanism. Therefore, the trigger voltage of embedded SCR structure can be significantly reduced by substrate-triggered technique to ensure effective ESD protection. The It2 per micron of embedded SCR structure is as high as ~100mA/µm, without using the silicide-blocking process modification.

The TLP-measured I-V curves of I/O cells with or without embedded SCR structure under PS-mode ESD stress are compared in Fig. 5.10. Without the embedded SCR structure, the ESD current at the input pad under PS-mode ESD stress is discharged through the silicide-blocking GGNMOS by snapback breakdown. The trigger voltage (snapback breakdown voltage) of GGNMOS is 4.3V, and the It2 of silicide-blocking GGNMOS with dimension W/L= 180/0.18 (µm/µm) is 1.6A. However, the trigger voltages of input cell with embedded SCR structures I and II under PS-mode ESD stress are only 3.44V and 2.5V,

respectively. In addition, the It2 of input cell with embedded SCR structure under PS-mode ESD stress can be increased to ~3A. From the measured results, the new proposed I/O cells with embedded SCR structure have lower trigger voltage, lower clamping voltage level, smaller turn-on resistance, and higher ESD robustness, as compared with the traditional I/O cells. Therefore, the ESD level of I/O cell can be efficiently improved by inserting the embedded SCR structure in I/O cell.

The TLP-measured I-V curves of the input pad under PS-mode ESD stress with or without silicide blocking on the input pMOS and nMOS devices are shown in Fig. 5.11. The It2 of the input pad under PS-mode ESD stress with silicide blocking on pMOS and nMOS devices is

~3A, and that without silicide blocking is ~2A. Whereas, the embedded SCR structures are fully silicided in these I/O cells. From the measured I-V curves, there is a distinct change of slope in the high current stress region, because the clamping voltage on the pad reaches the triggering voltage of the nMOS to cause a decrease on the turn-on resistance. With smaller turn-on resistance of fully silicided nMOS, the total turn-on resistance of the input pad under PS-mode ESD stress can be effectively reduced by input cell with fully silicided process. But with the fully silicided process, the It2 is dropped because the input nMOS device can sustain less ESD current when the parasitic npn bipolar transistor is triggered on. From the electrical measurements after the input pad under PS-mode ESD stress, the input pad is shorting to ground to indicate that the ESD damages are located at the input nMOS device. Therefore, with lower clamping voltage, the I/O cell with embedded SCR structure II is the design suggestion for fully silicided process.

The TLP-measured I-V curves of the I/O cells with embedded SCR structures I and II under NS-mode ESD stress are shown in Fig. 5.12. The It2 of input pad under NS-mode ESD stress with embedded SCR structure I is 4A, and that with embedded SCR structure II is 3A.

The I/O cell with embedded SCR structure I under NS-mode ESD stress has a higher It2 current, because the p+ pickup in the layout with a close-loop ring causes a larger effective turn-on area (parasitic diode of nMOS) for ESD current discharging. For the I/O cell with embedded SCR structure II under NS-mode ESD stress, there is a change of slope at high current stress region. The parasitic npn bipolar transistor of nMOS device is suspected to be triggered on to discharge ESD current from source (collector) to drain (emitter) to cause the decrease on the turn-on resistance.