ESD Protection Designs for Mixed-Voltage I/O Interfaces

1.2.1 Substrate-Triggered Stacked-NMOS Device

To improve the turn-on uniformity among the multiple fingers of CMOS output buffer, the substrate-triggered designs [56]-[58] have been reported to increase ESD robustness of the large-device-dimension nMOS. With the substrate-triggered technique, the substrate-triggered stacked-nMOS device [27] for mixed-voltage I/O interfaces is proposed and verified in Chapter 2 in this thesis. The ESD robustness of mixed-voltage I/O circuits can be effectively improved by this design without occupying extra silicon area to realize the additional stand-alone ESD protection device into the I/O cells.

1.2.2 Extra ESD Device between I/O pad and VSS

To improve ESD level of the mixed-voltage I/O circuits, the extra ESD device was added between I/O pad and VSS power line [59], [60]. The ESD current at the I/O pad under PS-mode ESD stress is designed to be directly discharged through this additional ESD device to the grounded VSS. The ESD current at the I/O pad under the PD-mode ESD stress can be discharged through this ESD device to VSS power line, and then through the parasitic diode of power-rail ESD clamp circuit to the grounded VDD.

One ESD protection design with the additional substrate-triggered lateral n-p-n BJT device has been used to protect the mixed-voltage I/O circuits in a fully salicided, 0.35-µm, thin-epi CMOS process [59]. The ESD protection design with substrate-triggered circuit and

the lateral n-p-n BJT device for the mixed-voltage I/O circuits is re-drawn in Fig. 1.9(a). The substrate-triggered circuit should meet the design constraints for providing effective ESD protection to the mixed-voltage I/O circuits, but without suffering the gate-oxide reliability issue. In this design, the substrate-triggered circuit is mainly composed of the diode string and a pMOS Mp1 to provide the substrate current for triggering on the lateral n-p-n BJT during ESD stress. A positive feedback network is formed with Mp2, Mn1, and R1, which maintains Mp1 in a highly conductive state to provide the substrate current during ESD stress.

Moreover, to improve the turn-on efficiency of lateral n-p-n BJT device in a thin-epi CMOS process with much smaller substrate resistance (Rsub), the device structure of lateral n-p-n BJT is specifically designed in Fig. 1.9(b). The lateral n-p-n BJT device consists of an n+

diffusion (emitter), an n-well (collector), and a p+ diffusion as its base. A dummy gate is formed between the p+ base and n+ emitter regions. The collector n-well encloses a portion of the p+ base region. In this design, the HBM ESD level of the mixed-voltage I/O circuits has been verified greater than 2kV in a fully-salicided thin-epi CMOS process.

Another ESD protection design, by using the additional stacked-nMOS triggered silicon controlled rectifier (SNTSCR), has been reported to protect the mixed-voltage I/O circuits [60]. The ESD protection design with the additional SNTSCR device for protecting the mixed-voltage I/O circuits is shown in Fig. 1.10(a). The device structure of SNTSCR and the corresponding ESD detection circuit are shown in Fig. 1.10(b). The ESD detection circuit, designed by using the gate-coupled technique with consideration of the gate-oxide reliability issue, is used to provide suitable gate bias to trigger on the SNTSCR device under ESD stress condition. On the contrary, this ESD detection circuit must keep the SNTSCR off when the IC is under normal circuit operating condition. During normal circuit operating condition, the Mn3 in Fig. 1.10(b) acts as a resistor to bias the gate voltage (Vg1) of Mn1 at VDD. But, the gate of Mn2 is grounded through the resistor R2 and Mn4. So, all the devices in the ESD protection circuit can meet the electrical-field constraint of gate-oxide reliability under normal circuit operating condition. Under PS-mode ESD stress condition, the Mp1 is turned on but Mn3 is off since the initial voltage level on the floating VDD line is ~0V. The capacitors C1 and C2 are designed to couple ESD transient voltage from the I/O pad to the gates of Mn1 and Mn2, respectively. The coupled voltage should be designed greater than the threshold voltage of nMOS to turn on Mn1 and Mn2 for triggering on the SNTSCR device, before the devices in the mixed-voltage I/O circuit are damaged by ESD stress. With the gate-coupled circuit technique, the trigger voltage of SNTSCR can be significantly reduced,

so the SNTSCR can be quickly triggered on to discharge ESD current. By changing the connection of the ESD protection circuit from the I/O pad to the floating n-well of the pull-up pMOS in the mixed-voltage I/O circuit, the SNTSCR device can have a high enough noise margin to the overshooting glitch on the I/O pad, during the normal circuit operating condition. From the experimental results in a 0.35-µm CMOS process, the HBM ESD level of the mixed-voltage I/O circuits with this ESD protection design has been greatly improved up to 8kV, as compared with that (~2kV) of the original mixed-voltage I/O circuits with only stacked nMOS device.

1.2.3 Extra ESD Device between I/O pad and VDD

To improve ESD level of the mixed-voltage I/O circuits, the extra ESD device was added between I/O pad and VDD power line [61]-[63]. The ESD current at the I/O pad under PS-mode ESD stress is designed to be discharged through this additional ESD device to VDD power line, and then through the power-rail ESD clamp circuit to the grounded VSS. The ESD current at the I/O pad under the PD-mode ESD stress can be directly discharged through this additional ESD device to the grounded VDD.

Because the diode in forward-biased condition can sustain much higher ESD current, the diode string has been used for protecting the mixed-voltage I/O circuits [61], [62], or used to realize the power-rail ESD clamp circuit [64]. The ESD protection design with the diode string connected between the I/O pad and VDD power line for the mixed-voltage I/O circuits is shown in Fig. 1.11. The number of diodes in the diode string is determined by the voltage difference between the maximum input voltage at I/O pad and the VDD supply voltage. To reduce the turn-on resistance from I/O pad to VDD during ESD stress, the area of such diodes has to be scaled up by the number of the diodes in stacked configuration. The major concern of using the diode string for ESD protection in the mixed-voltage I/O circuits is the leakage current. While the mixed-voltage I/O circuit is operating at a high-temperature environment with a high-voltage input signal, the forward-biased leakage current from the I/O pad to VDD through the stacked diodes could trigger on the parasitic vertical p-n-p BJT devices in the diode string. The Darlington bipolar amplification of these parasitic p-n-p BJT devices in the diode string will induce a large leakage current into the substrate. In Fig. 1.11, an additional snubber diode (SD) was used to reduce the leakage current due to the Darlington bipolar amplification in the diode string [61], [62].

device connected between I/O pad and VDD, has been designed to protect the mixed-voltage I/O circuits [63], as that shown in Fig. 1.12. In this ESD protection design, the pMOS Mp1 acting as ESD clamp device should be kept off to avoid the leakage current path during normal circuit operating condition. Under PD-mode ESD stress condition, the parasitic lateral p-n-p BJT in the device structure of Mp1 is turned on to discharge ESD current. In the 3.6V/5V mixed-voltage IC application, when the input voltage at I/O pad is 0V, the n-well voltage and gate voltage of Mp1 is clamped at VDD (3.6V) through the turn-on of Mp2 and Mp4. When the input voltage at I/O pad is 5V, the n-well voltage of Mp1 is maintained at 5-Vd (where Vd is the cut-in voltage of the parasitic drain-to-well diode), and the gate voltage of Mp1 is clamped at 5V through the turn-on of Mp3. Therefore, this design can meet the gate-oxide reliability constraints without leakage current path from I/O pad to VDD during normal circuit operating condition. Under ESD stress condition, the parasitic lateral p-n-p BJT in Mp1 is turned on to discharge ESD current by avalanche breakdown. Such a gated p-n-p BJT should be designed to effectively clamp the overstress ESD pulse without causing ESD damage in the mixed-voltage I/O circuits.

1.2.4 ESD Protection Design with ESD Bus

The whole-chip ESD protection scheme by using the additional ESD bus for the IC with power-down-mode application is proposed in Chapter 3 in this thesis [31]-[33]. Such design concept with ESD bus can be used to form the ESD protection network for the mixed-voltage I/O circuits, as shown in Fig. 1.13. The additional ESD bus line is realized by a wide metal line in CMOS IC [65]. The ESD bus is not directly connected to an external power pin, but biased to VDD through the diode D1 in Fig. 1.13. The diode D1 connected between the VDD power line and ESD bus is also used to block the leakage current path from the I/O pad to VDD during normal circuit operating condition with a high-voltage input signal. The diode Dp is connected between I/O pad and ESD bus, whereas the diode Dn is connected between VSS power line and I/O pad. One (the first) power-rail ESD clamp circuit is connected between VDD power line and VSS power line. Another (the second) power-rail ESD clamp circuit is connected between the ESD bus and VSS power line. The second power-rail ESD clamp circuit connected between ESD bus and VSS power line should be designed with high-voltage-tolerant constraints without suffering the gate-oxide reliability issue. The ESD current at the I/O pad under PS-mode ESD stress can be discharged through the diode Dp to

The ESD current at the I/O pad under the PD-mode ESD stress can be discharged through the diode Dp to the ESD bus, the second power-rail ESD clamp circuit to VSS power line, and then through the parasitic diode of the first power-rail ESD clamp circuit to the grounded VDD. With the turn-on-efficient power-rail ESD clamp circuits, high ESD level for the mixed-voltage I/O circuits can be achieved by this ESD protection scheme with ESD bus.

1.2.5 Special Applications

One of the mixed-voltage circuit applications, such as the interface in ADSL, has the input signals with voltage level higher than VDD and lower than VSS. This application limits the ESD diodes connected between the input pad and VDD/VSS power lines. To meet such mixed-voltage I/O interface, the SCR device with floating p-well structure in an n-substrate CMOS process has been used as on-chip ESD protection device [66]. However, the SCR device with a floating well structure is very sensitive to latchup [53], [67]. The mixed-voltage I/O interfaces in the system applications often meet serious overshooting or undershooting signal transition, which could trigger on the SCR device in the ESD protection circuit of I/O pad to induce latchup troubles to the chip [66]. A new ESD protection design, by using the low-voltage-triggered p-n-p (LVTPNP) device, has been proposed to protect such I/O interfaces with input voltage level higher than VDD and lower than VSS [68], as shown in Fig. 1.14. Comparing to the traditional p-n-p device in CMOS process, the LVTPNP device with a lower breakdown voltage by avalanche breakdown across the p+/n-well or n+/p-sub junctions provides effective discharging path to protect the mixed-voltage I/O interfaces against ESD stresses. During normal circuit operation condition, the LVTPNP device is kept off without causing any leakage current path. In cooperating with the power-rail ESD clamp circuit, the ESD current is discharged through the LVTPNP device by avalanche breakdown under four modes of ESD stresses. The ESD robustness of the LVTPNP device can be further improved by layout optimization.

For high-frequency and analog circuit applications, the high-voltage-tolerant ESD protection design should meet the constraint of low parasitic capacitance. The traditional analog ESD protection with double diodes connected between I/O pad and VDD/VSS power lines [69] cannot meet the high-voltage tolerant requirement. A high-voltage-tolerant ESD protection design, by using the forward-biased diode in series with the stacked-nMOS device, has been reported for analog ESD protection to reduce the input parasitic capacitance [70], as

junction capacitance of D1 plus the junction capacitance of D2. The diodes D1 and D2 can be drawn with small layout area, because the ESD current is discharged through these diodes under forward-biased condition. Therefore, the total parasitic input capacitance seen by the analog pin was reduced. The gates of Mn1 and Mn3 are connected to VDD to meet the gate-oxide reliability. The gates of Mn2 and Mn4 are grounded by the dynamic-floating-gate technique [71] to improve turn-on uniformity among the multiple fingers of the stacked nMOS device. The ESD current at the I/O pad under PS-mode ESD stress can be discharged through the diode D1 and the parasitic n-p-n BJT of stacked nMOS (Mn3 and Mn4) to the grounded VSS. The ESD current at the I/O pad under PD-mode ESD stress can be discharged through the diode D1 and the parasitic n-p-n BJT of stacked nMOS (Mn1 and Mn2) to the grounded VDD. Because the ESD current is discharged through the stacked-nMOS device by snapback breakdown in this design, the turn-on efficiency and ESD robustness of stacked-nMOS devices (Mn1 ~ Mn4) need to be further improved by the additional ESD-implantation process [72].