CHAPTER 2 ESD PROTECTION DESIGN FOR MIXED-VOLTAGE
2.4 Summary
To improve ESD robustness of the stacked-nMOS device in the mixed-voltage I/O circuit, the stacked-nMOS device with new proposed substrate-triggered circuit, has been designed and successfully verified in a 0.25-µm salicided CMOS process. The I-V characteristics of stacked-nMOS device with substrate-triggered technique have been measured to verify its effectiveness. By using this substrate-triggered design, the trigger voltage of the stacked-nMOS device can be reduced from the original 8.5V to become 5.3V to ensure effective protection for the mixed-voltage I/O circuits. The HBM ESD level of the
mixed-voltage I/O buffer with a stacked-nMOS of 240-µm channel width can be improved from the original 3.4kV up to 5.6kV by the substrate-triggered circuit. Without using the thick gate oxide, this new proposed ESD protection design is very useful in the sub-quarter-micron CMOS processes for effectively protecting the mixed-voltage interface circuits on the input and output pins.
TABLE 2.1
HBM ESD robustness of the mixed-voltage I/O buffers
with or without the proposed substrate-triggered circuit under a fixed device dimension.
Original Mixed-Voltage I/O Buffer
Mixed-Voltage I/O Buffer +
Substrate-Triggered Circuit
PS-Mode VSS(+)
NS-Mode VSS(-)
PD-Mode VDD (+)
ND-Mode VDD (-) HBM ESD
Stress I/O
Circuits
2.1kV 6.4kV 3.1kV 3.9kV
3kV 6.4kV 3.3kV 4kV
Pull-up PMOS W/L = 240/0.5 (µm) Stacked-NMOS W/L = 120/0.5 (µm) with Silicide-Blocking
Silicide-Blocking
(a)
n+ n+ n+ n+ n+
P-substrate
VG1 VG1 VG2
VG2 PAD
GND GND
STI
p+ STI p+
P-well
GND GND
(b)
Fig. 2.1 (a) The finger-type layout pattern, and (b) the corresponding cross-sectional view, of the stacked-nMOS device for mixed-voltage I/O circuit in a p-substrate CMOS process.
Device Channel Width (µm)
Device Channel Width= 120 µm In 0.25-µm CMOS process
(b)
Fig. 2.2 Comparisons of HBM ESD robustness of the stacked-nMOS device with or without the silicide-blocking process, under (a) different channel widths, and (b) different poly-to-poly spacings, of the stacked-nMOS device fabricated in a 0.25-µm CMOS process.
Silicide-Blocking
(a)
STI n+
P-substrate
n+ n+ p+
STI
n+ n+
n+
N-well N-well
VG1 VG1 VG2
VG2 GND
GND Itrig
STI p+
STI
p+ STI
STI
P-Well
GND GND
PAD
(b)
Fig. 2.3 (a) The finger-type layout pattern, and (b) the corresponding cross-sectional view, of the substrate-triggered stacked-nMOS device for mixed-voltage I/O circuit in a p-substrate CMOS process.
Fig. 2.4 The schematic circuit diagram of the substrate-triggered stacked-nMOS device with substrate-triggered circuit for the mixed-voltage I/O circuits.
STI
Fig. 2.5 The cross-sectional view of the substrate-triggered stacked-nMOS device with substrate-triggered circuit for the mixed-voltage I/O circuits.
Fig. 2.6 The modified design of the substrate-triggered stacked-nMOS device with substrate-triggered circuit for the mixed-voltage I/O circuits without generating extra additional capacitance to the I/O pad.
(a)
5 5.5 6 6.5 7 7.5 8 8.5 9
0 1 2 3 4 5 6 7 8
Itrig (mA)
Trigger Voltage (V)
(b)
Fig. 2.7 (a) The measured I-V characteristics of the substrate-triggered stacked-nMOS device with different substrate-triggered currents (Itrig). (b) The relation between the trigger voltage of the stacked-nMOS device and the substrate-triggered current (Itrig).
0
Fig. 2.8 The TLP-measured I-V curves of the stacked-nMOS device with different substrate-triggered currents.
0.0
Fig. 2.9 The dependence of It2 level on the substrate-triggered current (Itrig) under the different channel widths of substrate-triggered stacked-nMOS device.
1.0E-12 1.0E-11 1.0E-10 1.0E-09 1.0E-08
0 0.5 1 1.5 2 2.5 3
Voltage (V)
C u rr e n t (A )
Mixed-Voltage I/O Buffer with Substrate-Triggered Circuit
Mixed-Voltage I/O Buffer VDD= 2.5V
VSS= 0 V
Fig. 2.10 Comparison of the leakage currents of the mixed-voltage I/O buffers with or without the proposed substrate-triggered circuit. The mixed-voltage I/O buffer in this measurement has a channel width of 240 µm in the stacked nMOS and a channel width of 480 µm in the pull-up pMOS.
1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06
25 45 65 85 105 125
Temperature (°C )
Leakage Current (A) Mixed-Voltage I/O Buffer
Mixed-Voltage I/O Buffer with Substrate-Triggered Circuit VDD= 2.5 V
VSS= 0 V Vpad= 3.3 V
Fig. 2.11 The leakage currents of the mixed-voltage I/O buffers with or without the substrate-triggered circuit under different temperatures.
0.0 1.0 2.0 3.0 4.0 5.0 6.0
0 50 100 150 200 250 300
Stacked-NMOS Channel Width (µm)
HBM VESD (kV)
Mixed-Voltage I/O Buffer with Substrate-triggered Circuit
Mixed-Voltage I/O Buffer
with Silicide-Blocking
Increase
~65%
Fig. 2.12 The positive-to-VSS (PS-mode) HBM ESD levels of the mixed-voltage I/O buffers with or without the substrate-triggered circuit, realized in a 0.25-µm CMOS process with silicide-blocking process.
CHAPTER 3
ESD PROTECTION DESIGN FOR IC WITH POWER-DOWN-MODE OPERATION
For IC with power-down-mode operation, the on-chip ESD protection circuits will meet more design constraints and difficulties. In this chapter, three new ESD protection schemes for CMOS IC with power-down-mode operation are proposed. By adding a VDD ESD bus line and diodes, the ESD protection design can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the ESD protection design has no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. These new ESD protection designs for IC with power-down-mode operation has been successfully designed and verified in a 0.35-µm silicided CMOS process [31]-[33].
Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition [33].
3.1 New ESD Protection Schemes for IC with Power-Down-Mode Operation
3.1.1 ESD Protection Scheme I
The proposed ESD protection scheme I for the IC with power-down-mode operation is shown in Fig. 3.1 with the additional ESD bus line (VDD_ESD), which is realized by wide metal line in CMOS IC. The VDD_ESD bus line is not directly connected to an external power supply pin. The diode D1 is connected between the VDD power line and VDD_ESD bus line to block the leakage current path from the input pad to VDD when the power of VDD is off. The diode D2 is connected between the VDD power line and the source of output
power of VDD is off. The VDD_ESD bus line is not connected to the source of Mp_out in this scheme, because Mp_out may be turned on. The gate voltage of Mp_out will be dropped down and induces leakage current between I/O pads when the power of VDD is off. With the new proposed ESD protection scheme, the leakage current or malfunction issues for the IC with power-down-mode operation can be avoided. The diode D3 is connected between the output pad and VDD_ESD bus line for ESD protection purpose. One power-rail ESD clamp circuit is connected between VDD power line and VSS power line. A second power-rail ESD clamp circuit is connected between VDD_ESD bus line and VSS power line.
In the typical mixed-voltage I/O buffer, the output pMOS, connected from the I/O pad to the VDD power line, has self-biased circuits for tracking its gate and n-well voltages to avoid the leakage current path from the I/O pad to VDD when an over-VDD external signal is applied to the I/O pad [16]. However, during the power-down-mode operation, the tracking circuits will not function because the power of VDD is off. The channel of output pMOS cannot be kept off when the external voltage level on the output pad is high; therefore the leakage current may be induced from the output pad to VDD when the power of VDD is off.
By using the new proposed ESD protection scheme, the leakage current path from the I/O pad to VDD can be completely blocked by the diode D2 during the power-down-mode operation.
Although the output signal cannot be pulled up to VDD (kept at VDD-Vd, where Vd is the cut-in voltage of the diode D2) during normal circuit operating condition, it can be further improved with additional output-swing improvement circuit.
The ESD current discharging paths of the input pad under PS-mode ESD stress condition, the output pad under PS-mode ESD stress condition, the input pad under PD-mode ESD stress condition, and the output pad under PD-mode ESD stress condition are shown in Figs. 3.2(a)
~ 3.2(d), respectively. The ESD current at the input (or output) pad under PS-mode ESD stress can be discharged through the parasitic diode of Mp_in (or the diode D3) to the VDD_ESD bus, and then through the ESD clamp circuit from the VDD_ESD bus to the grounded VSS power line. The ESD current at the input (or output) pad under the PD-mode ESD stress can be discharged through the parasitic diode of Mp_in (or the diode D3) to VDD_ESD bus line, the ESD clamp circuit to VSS power line, and then through the parasitic diode of ESD clamp circuit to the grounded VDD power line. The negative ESD current at the input (or output) pad under the NS-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to ground. The negative ESD current at the input (or output) pad under the ND-mode ESD stress can be discharged through the parasitic diode of Mn_in (or
Mn_out) to VSS power line, and then discharged through the VDD-to-VSS ESD clamp circuit to the grounded VDD power line. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed ESD protection scheme.
3.1.2 ESD Protection Scheme II
The proposed ESD protection scheme II for the IC with power-down-mode operation is shown in Fig. 3.3. The design concept is similar to that of the ESD protection scheme I. In ESD protection scheme II, the VDD_ESD bus line is separated into input stage and output stage by the diode D3. The VDD ESD bus line of output stage is connected to the source of output pMOS (Mp_out). The diode D1 is connected between the VDD power line and VDD_ESD bus line to block the leakage current path from the input pad to VDD when the power of VDD is off. The diode D2 is connected between the VDD power line and the source of Mp_out to block the leakage current path from the output pad to VDD when the power of VDD is off. The gate voltage of Mp_out will be dropped down to induce leakage current between I/O pads when the power of VDD is off. The diode of D3 is used to block the leakage current between the I/O pads. One power-rail ESD clamp circuit is connected between VDD power line and VSS power line. A second power-rail ESD clamp circuit is connected between VDD_ESD bus line and VSS power line.
The ESD current at the input (or output) pad under PS-mode ESD stress can be discharged through the parasitic diode of Mp_in (or Mp_out) to the VDD_ESD bus, (the diode of D3,) and then discharged through the power-rail ESD clamp circuit from the VDD_ESD bus to the grounded VSS power line. The ESD current at the input (or output) pad under the PD-mode ESD stress can be discharged through the parasitic diode of Mp_in (or Mp_out) to VDD_ESD bus line, (the diode of D3,) the power-rail ESD clamp circuit to VSS power line, and then through the parasitic diode of power-rail ESD clamp circuit to the grounded VDD power line.
The negative ESD current at the input (or output) pad under the NS-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to ground. The negative ESD current at the input (or output) pad under the ND-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to VSS power line, and then discharged through the power-rail ESD clamp circuit to the grounded VDD power line. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed ESD protection scheme.
3.1.3 ESD Protection Scheme III
The proposed ESD protection scheme III for the IC with power-down-mode operation is shown in Fig. 3.4. The design concept is similar to that of the ESD protection scheme I. The diode D1 is connected between the VDD power line and VDD ESD bus line to block the leakage current path from the input or output pad to VDD, when the power of VDD is off.
The diode D3 in scheme II is replaced by the Mp1 in scheme III to block the leakage current between the I/O pads when the power of VDD is off. The gate of Mp1 is connected to the VDD power line. Therefore, Mp1 is turned off under the normal circuit operating condition.
Under power-down-mode operating condition, Mp1 is turned on to keep the Mp_out off. In addition, the power line of the pre-driver internal circuits which controlled the gate of Mp_out is connected to the VDD ESD bus line to avoid the leakage current from the pre-driver internal circuits to VDD power line, when the power of VDD is off. The ESD current at the input (or output) pad under PS-mode ESD stress condition can be discharged through the parasitic diode of Mp_in (or Mp_out) and the power-rail ESD clamp circuit between the VDD ESD bus line and the VSS power line to ground. The ESD current at the input (or output) pad under the PD-mode ESD stress condition can be discharged through the parasitic diode of Mp_in (or Mp_out) to VDD ESD bus line, the power-rail ESD clamp circuit to VSS power line, and then the parasitic diode of ESD clamp circuit to the grounded VDD power line. The negative ESD current at the input (or output) pad under the NS-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to ground. The negative ESD current at the input (or output) pad under the ND-mode ESD stress can be discharged through the parasitic diode of Mn_in (or Mn_out) to VSS power line, and then discharged through the power-rail ESD clamp circuit to the grounded VDD power line. The four modes of ESD stresses on the I/O pads can be safely protected by this new proposed ESD protection scheme.
Therefore, with the new proposed ESD protection schemes, the leakage current or malfunction issues for the IC with power-down-mode operation can be avoided. The internal circuits of CMOS IC can be fully protected against ESD damage by the new proposed ESD protection schemes.
3.1.4 Layout Consideration
For saving the layout area, the VDD_ESD bus line in the proposed ESD protection schemes can be realized by the different parallel metal layer, which overlaps the VDD power
line. The junction perimeter of the diodes (D1, D2, and D3) in the proposed ESD protection schemes can be drawn with small layout area, because the ESD current is discharged through these diodes with the forward-diode path. The device dimension of Mp1 in scheme II can be adjusted with less impact on ESD performance. In addition, it’s important to note that the location of power-rail ESD clamp circuit connected between VDD_ESD bus line and VSS power line is an important factor to implement the ESD protection scheme II. Because the ESD bus line is separated into input stage and output stage by the diode D3, the power-rail ESD clamp circuit must be placed in the input stage to provide the ESD current discharging path for input pad under ESD stress.
3.2 Experimental Results
The testchip with traditional and new proposed ESD protection schemes had been fabricated in a 0.35-µm silicided CMOS process. Fig. 3.5 shows the layout view of the new proposed ESD protection scheme I. Some inverters are connected from the input pad to the output pad, being served as the internal circuits for function verification of this testchip. The input ESD protection devices are realized by the gate-connected-to-source pMOS and gate-grounded nMOS with both the device dimensions (W/L) of 490/0.5 (µm/µm). The output ESD protection devices are realized by the output buffer of pMOS and nMOS with the same device dimensions. The layout parameters of ESD protection devices and output buffers are drawn according to the foundry’s ESD rules with the silicide-blocking mask. In the proposed ESD protection schemes, the junction perimeter of the diodes (D1, D2, and D3) is drawn as 50µm. In the proposed ESD protection scheme III, the device dimension (W/L) of Mp1 is drawn as 20/0.5 (µm/µm). The power-rail ESD clamp circuit is realized by the substrate-triggering field-oxide device (STFOD) [76], [77] to have high enough ESD level in a limited layout area, as shown in Fig. 3.6. The device dimensions for the power-rail ESD clamp circuit are drawn as R=55.3kΩ, C=14.2pF, W/L of Mp=100µm/1.2µm, W/L of Mn=20µm/1.2µm, and W/L of STFOD=232.8µm/1µm.
3.2.1 Leakage Current
The leakage currents at the input pad of the traditional and new proposed ESD protection
current is measured by applying a voltage ramp from 0 to 3.3V to the input pad under the bias condition of 3.3-V VDD and 0-V VSS. In Fig. 3.7(a), the leakage currents at the input pad of traditional ESD protection scheme, new proposed ESD protection schemes I, II, and III are 109pA, 134pA, 132pA, and 122pA, respectively, with a 3.3-V signal applying to the input pad. From the measured results, the new proposed ESD protection schemes do not induce any extra leakage current under normal circuit operating condition.
The leakage currents at input pad and output pad of the traditional and new proposed ESD protection schemes under power-down-mode operating condition are measured and compared in Figs. 3.7(b) and 3.7(c), respectively. The leakage current is measured by applying a voltage ramp from 0 to 3.3V to the input or output pad under the bias condition of 0-V VDD and 0-V VSS. From the measured results, the leakage currents at the input pads (output pads) of the new proposed ESD protection schemes are only ~130pA in Fig. 3.7(b) (~300pA in Fig.
3.7(c)), when a 3.3-V signal is applied to the input pad (output pad). On the contrary, the traditional ESD protection scheme has a very high leakage current of up to several mA when the input or output voltage is only increased to 0.7V. The leakage current in the new proposed ESD protection scheme has been successfully blocked by the diode of D1 or D2. The experimental results have verified that the new proposed ESD protection schemes can avoid the leakage current from the I/O pin to VDD power line under the power-down-mode operating condition.
3.2.2 Function Verification
The measurement setup to verify the function of I/O cells with the new proposed ESD protection schemes, or the traditional ESD protection scheme, under normal circuit operating condition and power-down-mode operating condition is shown in Fig. 3.8. To verify the function among the different designs under normal circuit operating condition, a 0-to-3.3 V voltage pulse with a rise time of 20 ns is applied to the input pad under the bias condition of 3.3-V VDD and 0-V VSS. In addition, to verify the function among the different designs under power-down-mode operating condition, a 0-to-3.3 V voltage pulse with a rise time of 20 ns is applied to the input pad under the bias condition of 0-V VSS but VDD is floating.
Figs. 3.9(a) and 3.9(b) show the voltage waveforms on the input/output pad of the I/O cells with the traditional ESD protection scheme under normal circuit operating condition and power-down-mode operating condition, respectively. As shown in Fig. 3.9(a), the I/O cells
operating condition. However, under the power-down-mode condition, the voltage waveform on the output pad is dropped to a voltage level of ~1.4V, when the input voltage level is 0V,
operating condition. However, under the power-down-mode condition, the voltage waveform on the output pad is dropped to a voltage level of ~1.4V, when the input voltage level is 0V,