CHAPTER 3 ESD PROTECTION DESIGN FOR IC WITH
3.3 Output-Swing Improvement Circuit
Although the output signal of the new proposed ESD protection scheme was not pulled up to full-VDD voltage swing during normal circuit operating condition, it can be further improved with additional output-swing improvement circuit. This circuit block connecting between the VDD power line and VDD_ESD bus line in the ESD protection scheme II is shown in Fig. 3.11(a). The circuit diagram of output-swing improvement circuit is shown in Fig. 3.11(b). In this circuit, Mp1 is used as a pull-up device to achieve the full-VDD voltage swing of output signal. During normal circuit operating condition, Mp1 is always turned on.
Thus, the output signal can be pulled up to VDD by the turn-on of Mp_out controlled by the pre-driver circuits. Therefore, the device size of Mp1 is determined by the driving current of the output cell in a CMOS IC. During power-down-mode operating condition, Mp1 is turned off to avoid the leakage current path from the output pad to VDD. The Mn1 and Mp2 in this circuit are used to control the gate of Mp1 during normal circuit operating condition and power-down-mode operating condition, respectively. The gates of Mn1 and Mp2 are connected to the VDD power line. Therefore, Mp2 is turned off, and Mn1 is turned on to keep the gate voltage of Mp1 at ~0V under normal circuit operating condition. With the turn-on of Mp1, the output signal can be pulled up to full-VDD voltage swing under normal circuit operating condition. Under power-down-mode operating condition with the bias condition of 0-V VDD, Mn1 is turned off, and Mp2 is turned on to keep the Mp1 off. The bodies (n-well) of Mp1 and Mp2 are connected to the VDD_ESD bus line to avoid the leakage path of the parasitic diode under power-down-mode operating condition. Therefore, no extra leakage current will be induced under the power-down-mode operating condition. This output-swing improvement circuit has been fabrication with the new proposed ESD protection scheme in a 0.35-µm CMOS process to verify its effectiveness.
The leakage currents at I/O pads of new proposed ESD protection scheme II with output-swing improvement circuit under normal circuit operating condition and
power-down-mode operating condition are measured in Fig. 3.12. From the measured results, no extra leakage current is induced by adding output-swing improvement circuit in the new proposed ESD protection scheme under both normal circuit operating condition and power-down-mode operating condition.
Figs. 3.13(a) and 3.13(b) show the voltage waveforms on the input/output pad of the new proposed ESD protection scheme II with the output-swing improvement circuit under normal circuit operating condition and power-down-mode operating condition, respectively. As shown in Fig. 3.13(a), the output signal has been really pulled up to full-VDD voltage swing under normal circuit operating condition, when the input voltage level is 0V. In Fig. 3.13(b), the internal circuits can be really kept off under power-down-mode operating condition.
Therefore, the output signal of the proposed ESD protection scheme can be pulled up to VDD by the output-swing improvement circuit under normal circuit operating condition, without increasing any leakage current.
3.4 Summary
Three new ESD protection schemes without leakage current path for CMOS IC operating in power-down-mode condition has been successfully designed and verified in a 0.35-µm silicided CMOS process. Under the normal circuit operating condition, the I/O cells with the new proposed ESD protection schemes can be operated normally. Under the power-down-mode operating condition, the new proposed ESD protection schemes can provide the I/O pad without leakage path, and avoid triggering the internal circuits those should be “off”. High ESD robustness has been practically achieved in the testchip with these new proposed ESD protection schemes to sustain HBM ESD stress of up to 7.5kV in a 0.35-µm silicided CMOS process. Furthermore, the output signal of the new modified ESD protection schemes can be successfully pulled up to VDD again by the output-swing improvement circuit under normal circuit operating condition.
TABLE 3.1
HBM ESD robustness of the traditional ESD protection scheme and the new proposed ESD protection schemes.
>8kV
New Proposed Scheme II (Input Pin)
New Proposed Scheme I (Input Pin)
Internal Circuits Internal
Circuits
Power-Rail ESD Clamp Circuit Power-Rail ESD Clamp Circuit
Output Pad Input
Pad
VDD
VSS VDD_ESD
Mp_in Mp_out
Mn_in Mn_out
D1 D2
D3
R
(b)
Fig. 3.1 The new proposed ESD protection scheme I for the IC with power-down-mode operation.
Internal
(continue to next page, Fig. 3.2)
VSS
Fig. 3.2 The ESD current discharging paths of (a) the input pad under PS-mode ESD stress condition, (b) the output pad under PS-mode ESD stress condition, (c) the input pad under PD-mode ESD stress condition, and (d) the output pad under PD-mode ESD stress condition.
Internal Circuits Internal
Circuits Power-Rail ESD Clamp Circuit
O/P
VDD
VSS
VDD_ESD
Mp_in Mp_out
Mn_in Mn_out
D1 D3 D2
I/P R
Power-Rail ESD Clamp Circuit
Fig. 3.3 The new proposed ESD protection scheme II for the IC with power-down-mode operation.
Pre-driver Circuits Internal
Circuits
Power-Rail ESD Clamp Circuit Power-Rail ESD Clamp Circuit
O/P
I/P CircuitsInternal
VDD
VSS VDD_ESD
Mp_in Mp_out
Mn_in Mn_out
D1 Mp1
R
Fig. 3.4 The new proposed ESD protection scheme III for the IC with power-down-mode operation.
Input
Fig. 3.5 The layout view of the new proposed ESD protection scheme I fabricated in a 0.35-µm silicided CMOS process.
R
Fig. 3.6 The circuit diagram of power-rail ESD clamp circuit.
Input Voltage (V)
(continue to next page, Fig. 3.7)
Output Voltage (V)
Fig. 3.7 Comparison of the measured leakage currents at (a) the input pad under normal circuit operating condition, (b) the input pad under power-down-mode operating condition, and (c) the output pad under power-down-mode operating condition, of the traditional and new proposed ESD protection schemes.
Internal Circuits
Fig. 3.8 The measurement setup to verify the function of I/O cells with the new proposed ESD protection schemes, or the traditional ESD protection scheme, under normal circuit operating condition and power-down-mode operating condition.
Input Waveform
Output waveform
3.3 V
3.3 V 0 V
0 V
Normal Circuit Operation
VDD= 3.3V, VSS= 0V
3.3 V
3.3 V 3.3 V
(a)
Input Waveform
Output Waveform
3.3 V
1.4 V 0 V
0 V
1.4 V
VDD= floating, VSS= 0V
3.3 V 3.3 V
Power-down-mode Operation
(b)
Fig. 3.9 The measured voltage waveforms on the input/output pad of IC with the traditional ESD protection scheme under (a) normal circuit operating condition with VDD= 3.3V and VSS= 0V, and (b) power-down-mode operating condition with VDD= floating and VSS= 0V. (Y axis= 1V/Div., X axis= 200ns/Div.)
Input Waveform
Output Waveform
3.3 V
2.7 V 0 V
0 V
Normal Circuit Operation VDD= 3.3V, VSS= 0V 3.3 V
2.7 V
3.3 V
(a)
Input Waveform
Output Waveform 3.3 V
0 V
0 V
VDD= floating, VSS= 0V
3.3 V
Power-down-mode Operation
3.3 V
(b)
Fig. 3.10 The measured voltage waveforms on the input/output pad of IC with the proposed ESD protection scheme I under (a) normal circuit operating condition with VDD=
3.3V and VSS= 0V, and (b) power-down-mode operating condition with VDD=
floating and VSS= 0V. (Y axis= 1V/Div., X axis= 200ns/Div.)
Internal Circuits Internal
Circuits Power-Rail ESD Clamp Circuit
O/P
VDD_ESDMp_in Mp_out
Mn_in Mn_out
D1 D2
D3
I/P
RPower-Rail ESD Clamp Circuit
Output_Swing Improvement
Circuit
VDD
VSS
(a)
Mp1
Mp2
Mn1
VDD_ESD VDD
VSS
(b)
Fig. 3.11 (a) The output-swing improvement circuit connecting between the VDD power line and VDD_ESD bus line in the ESD protection scheme II. (b) The circuit diagram of output-swing improvement circuit.
Voltage (V)
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Leakage Current (A)
1e-12 1e-11 1e-10 1e-9 1e-8 1e-7 1e-6
Input Pad
Normal Circuit Operation (VDD=3.3V, VSS=0V)
Input Pad
Power-down-mode Operation (VDD=0V, VSS=0V) Output Pad
Power-down-mode Operation (VDD=0V, VSS=0V)
Fig. 3.12 The measured leakage currents at I/O pads of new proposed ESD protection scheme II with the output-swing improvement circuit under normal circuit operating condition and power-down-mode operating condition.
Input Waveform
Output Waveform
3.3 V
3.3 V 0 V
0 V
Normal Circuit Operation
VDD= 3.3V, VSS= 0V
3.3 V
3.3 V 3.3 V
(a)
Input Waveform
Output Waveform
3.3 V
0 V
0 V
VDD= floating, VSS= 0V 3.3 V
Power-down-mode Operation
3.3 V
(b)
Fig. 3.13 The measured voltage waveforms on the input/output pad of the proposed ESD protection scheme II with output-swing improvement circuit under (a) normal circuit operating condition with VDD= 3.3V and VSS= 0V, and (b) power-down-mode operating condition with VDD= floating and VSS= 0V. (Y axis= 1V/Div., X axis= 200ns/Div.)
CHAPTER 4
ESD PROTECTION DESIGN
IN HIGH-VOLTAGE CMOS PROCESS
When the high-voltage device is used as the power-rail ESD clamp device, the device is expected to be kept off in normal circuit operating condition. In the ESD stress condition, the ESD protection device should be triggered on to discharge ESD current. In this chapter, the double snapback characteristic in the high-voltage nMOSFETs has been investigated and analyzed by both measured and simulation results [44]. Furthermore, the holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup or latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-µm 40-V CMOS process to achieve the desired ESD level [45], [46].
4.1 Double Snapback Characteristics in High-Voltage NMOSFETs
4.1.1 Double-Snapback Characteristics
The DDD (Double Diffused Drain) MOS structure fabricated in a 0.35-µm 18-V CMOS process and LDMOS (Lateral Diffused MOS) structure fabricated in a 0.25-µm 40-V CMOS process are studied in this work. The TLP system with a pulse width of 100 ns and a rise time of ~10 ns [75] is used to measure the snapback I-V curves of the fabricated 18-V and 40-V nMOSFET devices. The TLP-measured I-V characteristics of 18-V and 40-V gate-grounded nMOS (GGNMOS) devices are shown in Figs. 4.1(a) and 4.1(b), respectively. The
figure. From the measured results, the double-snapback characteristics are found both in 18-V nMOSFET and 40-V nMOSFET. For the 18-V nMOSFET shown in Fig. 4.1(a), after the first snapback voltage at 22.2 V, the device snaps back to 8.5 V. Then, the device quickly goes into the second snapback, and the voltage drops to only ~5 V. The slope of the snapback curves is almost the same at first and second snapback states. For the 40-V nMOSFET shown in Fig. 4.1(b), after the first snapback voltage at 27.2 V (52 V in dc), the device snaps back to 23 V, from where the voltage strongly increases again. Then, the device goes into the second snapback, and the voltage drops to only ~7 V. In 40-V nMOSFET, the turn-on resistance of the first snapback state is much larger than that of the second snapback state.
4.1.2 Simulations and Analysis
The first snapback mechanism involves both avalanche breakdown and turn-on of the parasitic bipolar transistor [78]. For 40-V nMOSFET, the avalanche generation is initiated by the n+ buried layer (NBL)/p-well junction. Fig. 4.2(a) shows the current distribution in the 40-V nMOSFET under first snapback state, where the current path flows vertically into the NBL region. Due to the longer current path through lightly doped well region, the turn-on resistance is large at the first snapback state, as that shown in Fig. 4.2(b). When the current further increases, the device enters into high-injection condition and the Kirk effect [79]
occurs. The base push-out effect causes the maximum electric field to change from the NBL/p-well junction to the n+/n-well junction. Due to higher multiplication rate at this higher doped region, a strong snapback occurs to cause a low holding voltage. Fig. 4.2(b) shows the current distribution in the 40-V nMOSFET under the second snapback state. The current path changes from the vertical direction to the lateral direction, when the device switches from the first to the second snapback state. The turn-on resistance becomes much smaller when the current path flows in the lateral direction. For 18-V nMOSFET, the avalanche generation is initiated by the n-diffused-drain (NDD)/p-well junction. With shallower NDD diffusion in the device structure, the current path basically flows in the lateral direction at the first and second snapback states. Therefore, the turn-on resistance is almost the same at these two states. In addition, with shallower NDD diffusion, the first snapback state could be not obvious, because the maximum electric field changes from the NDD/p-well junction to the n+/NDD junction quickly.
The doping concentration and junction depth of lightly doped drain region (NDD for 18-V
nMOSFET and n-well for 40-V nMOSFET) are the major factors to influence double snapback characteristics. Because these factors directly affect the process of base push-out effect, which changes the maximum electric field from initial avalanche breakdown region to the n+/n- region. The increase of doping concentration and junction depth of lightly doped drain region will delay space-charge region edge moving toward n+/n- region, and therefore delay the device into the second snapback state.
4.2 High-Voltage ESD Protection Devices
4.2.1 TLP I-V Characteristics
Besides high-voltage nMOSFET device, SCR device, field-oxide (FOD) device, and high-voltage pMOSFET device fabricated in a 0.25-µm 40-V CMOS process are also studied in this work. The layout parameters of such ESD protection devices are drawn according to the foundry’s ESD rules with the silicide-blocking mask. The cross-sectional views and TLP-measured I-V characteristics of high-voltage gate-grounded nMOS (GGNMOS) device, SCR device, FOD device, and gate-VDD pMOS (GDPMOS) device are shown in Fig. 4.3 - Fig. 4.6, respectively. For high-voltage GGNMOS device in Fig. 4.3 The second breakdown current (It2) of GGNMOS device with 200-µm channel width is 2.7A. For high-voltage SCR device in Fig. 4.4(a), the characteristic of very low holding voltage and high ESD robustness has been found. As shown in Fig. 4.4(b), the holding voltage of SCR device is only ~4V and the It2 current of SCR device with 200-µm width is over 6A. For high-voltage FOD device structure shown in Fig. 4.5(a), the device is isolated by the n+ buried layer (NBL) from the common p-type substrate. The spacing from collector diffusion to emitter diffusion of FOD device is 6µm in this study. As shown in Fig. 4.5(b), the TLP-trigger voltage is 19.7V (50V in DC), and the holding voltage is ~16V. The It2 current of FOD device with 200-µm width is 0.5A. The difference on trigger voltages of the device measured by DC (HP4155) and TLP is caused by the transient-coupling effect through the parasitic capacitance of the device. The TLP is designed with a rise time of 10ns to simulate the HBM ESD event. The dV/dt transient voltage at the zapping node could be coupled into the device through the parasitic capacitance in the drain/bulk junction to lower the trigger voltage. For high-voltage GDPMOS device in Fig. 4.6(a), no snapback characteristic is found. The holding voltage of the device is larger
current of GDPMOS device with 200-µm channel width is only 0.06A, as that shown in Fig.
4.6(b). Therefore, GDPMOS is not suitable for on-chip ESD protection device in high-voltage CMOS ICs due to too low ESD robustness.
4.2.2 Transient Latchup Test
Transient latchup (TLU) test is used to investigate the susceptibility of the ESD protection devices to the noise transient or glitch on the power lines during normal circuit operating condition. The measurement setup for TLU test is shown in Fig. 4.7. The positive or negative charging voltage (Vcharge) on the energy storage capacitor (C1) generating the transient is used to trigger the device into the latch state [80]. A supply voltage of 40V was used to bias the device as normal circuit operating condition. The transient trigger source was connected directly to the device-under-test (DUT). The small resistance (R1) is used to protect the DUT, when the DUT is triggered on into the latch state. In addition, the diode (D1) in Fig. 4.7 is used to avoid the damage to the power supply during TLU test [80]. The voltage waveform on the DUT (at node Y) during TLU test is monitored by a digital oscilloscope with a sampling rate of 5G Hz in this experiment. The measured voltage waveforms on high-voltage GGNMOS device, SCR device, and FOD device under TLU test are shown in Fig. 4.8 - Fig.
4.10, respectively.
From the measured results, the devices are initially kept off before the transient trigger, therefore the voltage waveforms are initially kept at 40V. After the transient trigger, the snapback characteristic in the device can be triggered on to generate a low-holding-voltage state. The clamped voltage level of the devices in snapback breakdown condition is consistent with the holding voltage measured by TLP stress. In Fig. 4.8, the clamped voltage level of high-voltage GGNMOS device is ~7V due to the transient triggering with the capacitor charging voltage of 55V. The GGNMOS device is triggered into the second snapback state directly by the transient pulse. If such high-voltage nMOSFET is used in the power-rail ESD clamp circuit, the latchup-like issue between the power rails will occur, when the high-voltage nMOSFET is triggered on by the noise transient on the power lines.
In Fig. 4.9, the clamped voltage level of high-voltage SCR device is only ~4V due to the transient triggering with the capacitor charging voltage of only 44V. Although SCR device has the advantage of high ESD robustness, the latchup issue in high-voltage CMOS ICs becomes worse. Figs. 4.10(a) and 4.10(b) show the measured voltage waveforms of
high-voltage FOD device under TLU test with positive and negative charging voltages, respectively. Both positive and negative charging voltages can trigger the FOD device into the latch state. The clamped voltage level of FOD device is ~16V due to the transient triggering with the capacitor charging voltage of 47V or -10V. For negative charging voltage, the parasitic N-well/p-substrate junction between the power rails may be turned on initially, but it is turned off quickly due to the transient ringing voltage waveform. Finally, the FOD device is triggered into the holding state. Latchup-like issue is the concern by using single FOD device as the power-rail ESD clamp in high-voltage CMOS ICs.
From the power dissipation view, the device with a lower holding voltage is helpful to sustain much higher ESD current. However, the device may be triggered on by the noise transient or glitch on the power lines during normal circuit operating condition, especially under the system-level EMC/ESD zapping test. If the holding voltages of high-voltage ESD protection devices are smaller than the power supply voltage of normal circuit operating condition, the high-voltage CMOS ICs will be susceptible to the latchup or latchup-like danger in the system applications, which often meet the noise or transient glitch issues.
4.3 Design of Latchup-Free Power-Rail ESD Clamp Circuits
The NMOS and SCR devices have higher It2 than that of FOD device, but their holding voltages (~7V in NMOS, ~4V in SCR) are far away from the 40-V operating voltage level.
Such ESD protection devices with low holding voltage in power-rail ESD clamp circuits will cause serious latchup failure to high-voltage CMOS ICs. To overcome the latchup or latchup-like issue between the power rails in high-voltage CMOS ICs, a new stacked-field-oxide structure has been designed to increase the total holding voltage. The stacked-field-oxide structure with two cascaded FOD devices has been fabricated in a 0.25-µm 40-V CMOS process. The I-V characteristic and ESD robustness of stacked-field-oxide structure has been investigated by the TLP stress. The susceptibility of stacked-field-oxide structure to the noise transient during normal circuit operating condition has also been performed by the TLU test. Finally, a latchup-free power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and verified.
4.3.1 TLP I-V Characteristics
The measurement setup of single high-voltage FOD device and stacked-field-oxide structure under TLP stress is shown in Fig. 4.11(a). The TLP-measured I-V characteristics of
The measurement setup of single high-voltage FOD device and stacked-field-oxide structure under TLP stress is shown in Fig. 4.11(a). The TLP-measured I-V characteristics of