Organization of This Dissertation

To overcome the challenges in ESD protection design for power-rail ESD clamp circuits, analog I/O interface circuits, and cross-power-domain interface circuits in deep-submicron and nanoscale CMOS integrated circuits, several new designs are developed and verified in this dissertation. This dissertation comprises eight chapters. In Chapter 2, the comparison of the controlling circuit implemented with 1-stage or 3-stage inverters has been presented [43].

Then, the drain-contact-to-poly-gate spacing (D) of the main ESD clamp NMOS transistor has been also split in order to investigate the influence of this spacing on the ESD protection capability. In Chapter 3, an efficient ESD-transient detection circuit with capacitance coupling mechanism has been proposed to accomplish the desirable function on commanding the main ESD clamp NMOS transistor. A novel initial-on SCR design is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device in Chapter 4.

Chapter 5 further discusses optimizations on the initial-on SCR devices are presented [44]-[46]. The modified initial-on SCR device with merged layout style is also proposed to enhance its ESD protection capability. Besides ESD protection design for power-rail ESD clamp circuit, the comparison among different ESD protection designs for analog I/O

interface circuits is presented [47] in Chapter 6. A new active ESD protection design for the interface circuits between separated power domains is proposed [48] in Chapter 7. Chapter 8 gives the conclusions and future works of this dissertation. The outlines of each chapter are summarized below.

Chapter 2 presents the comparison between 1-stage and 3-stage inverters in the controlling circuits. The circuit performances of both controlling circuits in power-rail ESD clamp circuits are measured and compared under ESD-stress conditions and normal circuit operation conditions. On the other hand, the drain-contact-to-poly-gate spacing (D) of the main ESD clamp NMOS transistor has been also split from 0.25 μm to 2.0 μm in order to investigate the influence of this spacing on the ESD protection capability. Through the arranged combinations of different controlling circuits and main ESD clamp NMOS transistors in different layout styles, the influence can be thoroughly investigated from the characteristic and performance of each power-rail ESD clamp circuit in silicon. The optimized circuit scheme for controlling circuits and layout style for the main ESD clamp NMOS transistors can be suggested for using in the power-rail ESD clamp circuits.

In Chapter 3, an efficient ESD-transient detection circuit has been proposed and verified in 130-nm 1.2-V CMOS technology. This design abandons the feedback circuit techniques and adopts capacitance coupling mechanism to accomplish the desirable function on commanding the main ESD clamp NMOS transistor. Through experimental measurements, such as turn-on verification, transmission line pulse (TLP) stress, ESD stress, and fast power-on test, this power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit presents an excellent performance to meet the specified requirements.

According to the measured results, the new proposed ESD-transient detection circuit possesses the sufficient turn-on duration under the ESD-stress conditions and high mis-trigger and latch-on immunities under the fast power-on conditions.

In Chapter 4, a novel initial-on SCR design is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on SCR design is realized by circuit skill with the PMOS transistor and RC-based ESD-transient detection circuit in general CMOS processes. This initial-on SCR design, which is implemented by PMOS-triggered SCR device cooperated with RC-based ESD-transient detection circuit, also presents a high enough holding voltage in a fully-silicided 0.25-μm CMOS process to avoid latchup issues in normal circuit operation conditions. Such initial-on

SCR devices can achieve the whole-chip ESD protection scheme for input, output, power-rail ESD clamp circuit, and the ESD clamp cells between the separated power domains.

Chapter 5 presents further optimizations on the PMOS-triggered SCR devices. The modified PMOS-triggered SCR device with merged layout style is proposed to further enhance its ESD protection capability. In addition, NMOS transistors are also embedded into the SCR structures to implement NMOS-triggered SCR devices. The device characteristics of these two different MOS-triggered SCR devices are compared to optimize the on-chip ESD protection design in CMOS ICs. Moreover, the obvious differences on the Vh of NMOS-triggered SCR devices under DC and TLP measurements have been attributed to the current distributions through the parasitic npn bipolar transistor in the SCR device.

In Chapter 6, different ESD protection designs for the analog I/O pin are compared to find the optimal ESD protection circuit for the analog I/O interface circuit in 0.18-µm 1.8-V/3.3-V CMOS technology. In addition, the failure analyses on both 1.8-V and 3.3-V analog I/O pins are presented after ND-mode and PS-mode ESD stresses. In the ESD protection designs with MOS devices, ESD robustness is dominated by the ESD levels of GGNMOS or GDPMOS under the PS-mode or ND-mode ESD stresses. However, the failure mechanism is different from the ESD protection design with pure diodes under PS-mode or ND-mode ESD stresses. Besides, an unexpected failure mechanism has been found in the analog I/O pin with the pure-diode ESD protection circuit. The parasitic npn bipolar transistor formed by the N+ diode and the N-well guard ring structure provides the ESD current path during the ND-mode ESD stress, which causes a low ESD level to the analog I/O pin.

The cross-power-domain ESD issues are investigated in Chapter 7. First, a failure study in a 0.35-μm 3.3 V/5 V mixed-mode CMOS IC product with two separated power domains is presented. The ESD failure spots were specially observed at the interface circuits between the separated power domains after ND-mode MM ESD stress of 100 V. However, this IC product has 2-kV HBM ESD robustness in each ESD test combination of I/O pin to power/ground pins. Therefore, the efficient ESD protection designs should be applied on the interface circuits between the separated power domains against such cross-power-domain ESD stresses.

Secondly, several active cross-power-domain ESD protection designs were reviewed to compare their ESD protection strategies for interface circuits between separated power domains. Besides, one new active ESD protection design for the interface circuits between separated power domains has been also proposed to solve the interface circuit damages under cross-power-domain ESD stresses. This ESD protection design has been implemented by

PMOS and NMOS transistors with the ESD-transient detection function in a 0.13-μm 1.2-V CMOS technology. It can be rapidly triggered on and efficiently reduced the overstress voltages across the gate oxides of the MOS transistors of the receivers in interface circuits between separated power domains under the cross-power-domain ESD stresses. The proposed ESD protection design for the interface circuits between separated power domains has been successfully verified with 4-kV HBM and 400-V MM ESD robustness against cross-power-domain ESD stresses.

Chapter 8 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter.

Chapter 2

Evaluation on NMOS-Based Power-Rail ESD Clamp Circuits with Gate-Driven Mechanism

In this chapter, two different circuit schemes for the controlling circuit in power-rail ESD clamp circuit are compared. The circuit performances of two controlling circuits, which are respective implemented by 1-stage inverter and 3-stage inverters, in power-rail ESD clamp circuits are measured and compared under ESD-stress conditions and normal circuit operation conditions. In addition, the layout style of the main ESD clamp NMOS transistor has been also studied in order to investigate the influence of this spacing on the ESD protection capability. Through the eight arranged combinations of two different controlling circuits and main ESD clamp NMOS transistors in four different layout styles, the influence can be thoroughly investigated from the characteristic and performance of each power-rail ESD clamp circuit in silicon. Moreover, the impact of the fast power-on application [10], [11]

or the transient noise on power/ground lines [20], [21] on the power-rail ESD clamp circuits has been also discussed in this chapter. According to these experimentally measured results, the optimal circuit scheme for controlling circuit and layout style for the main ESD clamp NMOS transistor can be suggested for using in the power-rail ESD clamp circuit.

2.1. Power-Rail ESD Clamp Circuits with Different Controlling Circuits and Layout Styles for Main ESD Clamp NMOS

2.1.1. Influence of the RC-Time Constants

It has been studied and reported that the RC-time constants of the RC-based ESD-transient detection circuits made an impact on the ESD robustness of the power-rail ESD clamp circuits. In a previous work [49], all main ESD clamp NMOS transistors were drawn as the BFETs with the drain-contact-to-poly-gate spacings from 0.22 μm to 0.44 μm and no silicide blocking on the diffusions. The total channel widths of those BFETs were

identically 2000 μm. However, they occupied different silicon areas. According to the measured results in that previous work, the ESD robustness were not significantly improved or enhanced by increasing the RC-time constant from 0.1 μs to 1.0 μs. Furthermore, the longest RC-time constant of 1.0 μs could slightly induce some degradation on ESD robustness of the power-rail ESD clamp circuit. But, the drain-contact-to-poly-gate spacings have strong impact to ESD robustness of the NMOS-based power-rail ESD clamp circuits under the same RC-time constant. The ESD robustness can be efficiently increased by increasing the drain-contact-to-poly-gate spacings among all RC-time constants. However, the large drain-contact-to-poly-gate spacings will enlarge the total occupied silicon areas of the main ESD clamp NMOS transistors. Based on the practical applications of the standard I/O cell libraries, each I/O cell (such as input pin, output pin, VDD pin, and VSS pin) was usually required to possess a rigid cell space in order to easily and automatically arrange these pins in chip layout. In general, the VDD pin (or VSS pin) was included the power-rail ESD clamp circuit to provide the ESD protection between VDD and VSS. Therefore, the power-rail ESD clamp circuit which consists of the RC-based ESD-transient detection circuit, the controlling circuit, and the main ESD clamp NMOS transistor must be restrained into an established silicon area to match the rigid cell space. According to the measured results in that previous study [49], because the influences of the RC-time constant from 0.1 μs to 0.5 μs on ESD robustness were not significant, the RC-time constant has been fixed at 0.2 μs in this work to reduce the occupied silicon area of the resistor and capacitor in this testchip.

2.1.2. Controlling Circuits and Layout Styles

Both controlling circuits, which are the 1-stage inverter and the 3-stage inverters, are respectively arranged to command the main ESD clamp NMOS transistors with different drain-contact-to-poly-gate spacings. One of the main ESD clamp NMOS transistors has the layout style with minimized drain-contact-to-poly-gate spacing (D) and no silicide blocking (SB) on its diffusion, as shown in Fig. 2.1(a). This NMOS transistor, which is the Big FET (BFET), will be expected to have no snapback operation. However, another one has a totally different layout style with extended drain-contact-to-poly-gate spacing (D) and silicide blocking (SB) on its diffusion, as shown in Fig. 2.1(b). It is a traditional ESD clamp NMOS transistor with snapback operation. It has been proven that the parasitic npn bipolar transistor was turned on to induce the snapback operation in such ESD clamp NMOS transistor [4], [5].

The drain-contact-to-poly-gate spacings of the BFET and traditional ESD clamp NMOS

transistors are 0.25 μm and 2.0 μm, respectively. Besides, different layouts on the main ESD clamp NMOS transistor, called the modification design in this work, with a drain-contact-to-poly-gate spacing of 0.75 μm has been also implemented in the testchip with or without silicide blocking on its drain-side diffusion. Through such splits in layout, the influences of the drain-side equivalent resistance on circuit performance and ESD robustness can be used to judge the optimal layout style for the main ESD clamp NMOS transistor.

(a)

(b)

Fig. 2.1. The main ESD clamp NMOS transistor has (a) the BFET layout style with the drain-contact-to-poly-gate spacing (D) of 0.25 μm and no silicide blocking (SB) on its diffusions, and (b) the traditional layout style with the D of 2.0 μm and SB on its drain-side diffusions.

The eight designs of power-rail ESD clamp circuits from the combinations of the main ESD clamp NMOS transistor in different layout styles and the controlling circuit with different inverter stages have been drawn in the testchip for comparison, as shown in Table 2.1. For comparison purpose, the layout areas of the main ESD clamp NMOS transistors among those eight designs are kept the same in layout. Therefore, the total channel width of the traditional ESD clamp NMOS transistor is 624 μm, whereas that of the BFET is about 2600 μm. The total channel width of main ESD clamp NMOS transistor with the drain-contact-to-poly-gate spacing of 0.75 μm is 1144 μm. In addition, the RC time constant in those eight designs are all kept at 200 ns. This testchip has been fabricated in a 0.13-μm 1.2-V CMOS process.

Table 2.1

Eight Designs of the Power-Rail ESD Clamp Circuits Verified in this Work

2.2. Experimental Results in Component-Level Tests

2.2.1. DC Leakage Current

Power-rail ESD clamp circuits must be kept off to avoid unnecessary VDD-to-VSS leakage current under normal circuit operation conditions. However, the main ESD clamp

NMOS transistors always have huge device dimension to achieve the required ESD robustness. Thus, they will be some concern on leakage, especially in the nanoscale CMOS technology. The leakage currents of the power-rail ESD clamp circuits with controlling circuits of 1-stage inverter and 3-stage inverters in are shown in Figs. 2.2(a) and 2.2(b), respectively.

(a)

(b)

Fig. 2.2. DC leakage currents among the power-rail ESD clamp circuits of different designs with controlling circuit of (a) with 1-stage inverter and (b) 3-stage inverters.

There is no obvious difference on the leakage currents between the power-rail ESD clamp circuits with different controlling circuits under the identical main ESD clamp NMOS transistor. The leakage currents of BFET1 (or BFET2) are 0.5 μA under the VDD bias of 1.2 V, whereas those of Tradition1 (or Tradition2) are below 0.15 μA at the same VDD bias. In addition, no significant difference of the leakage currents is observed between the main ESD clamp NMOS transistor with or without silicide blocking (SB) on its diffusion, as illustrated in the measured results of Modification1 and Modification2 (or Modification3 and Modification4). According to the measured results, the leakage currents of Tradition1 and Trdition2 are 3-times less than those of BFET1 and BFET2 due to the large channel widths in BFET1 and BFET2. Therefore, the leakage current of the power-rail ESD clamp circuit is strongly dependent on the channel width of the main ESD clamp NMOS transistor.

2.2.2. Turn-On Verification under ESD-Like Stress Condition

To observe the turn-on efficiency among the different power-rail ESD clamp circuits, a 2.4-V ESD-like voltage pulse with 2-nano-seconds (ns) rise time is applied on the VDD terminal with VSS terminal grounded in each circuit. The voltage pulse with a rise time of 2 ns and duration of 600 ns generated from a pulse generator is used to simulate the fast rising edge of HBM ESD event [1]. The sharp-rising edge of the ESD-like voltage pulse will be detected by the RC-based ESD-transient detection circuit and then to turn on the main ESD clamp NMOS transistor. When the main ESD clamp NMOS is turned on, the voltage waveform on VDD node will be clamped as the measured results shown in Figs. 2.3(a) and 2.3(b). Tradition1 and BFET1, both of which have 1-stage inverter in the controlling circuits, presented similar voltage waveforms under 2.4-V ESD-like voltage pulses. Besides, Tradition2 clamped the overshoot voltage pulses to a lower voltage level during the first 300 ns of the ESD-like voltage pulses. However, the BFET2 performs an excellent ability to clamp the overshoot voltage pulse to a much lower voltage level, as shown in Fig. 2.3(a). On the other hand, the influences of drain-side silicide blacking on turn-on behaviors of the power-rail ESD clamp circuits have been measured in Fig. 2.3(b). Under the same drain-contact-to-poly-gate spacings of 0.75 μm, Modification3 exhibits the best turn-on efficiency among other designs. Besides, the turn-on efficiency of Modification4 is higher than that of Modification1 and Modification2 during the first 350-ns pulse duration.

According to the measured results, the controlling circuit with 3-stage inverters seems to be an optimal candidate to implement the main ESD clamp NMOS transistor with BFET layout

style in the power-rail ESD clamp circuit. The controlling circuit would hold a dominant factor on the turn-on behaviors of the power-rail ESD clamp circuit.

(a)

(b)

Fig. 2.3. The measured voltage waveforms of (a) Tradition1, Tradition2, BFET1, and BFET4, and of (b) Modification1, Modification2, Modification3, and Modification4, under 2.4-V ESD-like voltage pulses with 2-ns rise time.

2.2.3. TLP I-V Characteristics and HBM ESD Robustness

The Transmission Line Pulse (TLP) [50] measured I-V characteristics of the power-rail ESD clamp circuits are shown in Figs. 2.4(a), 2.4(b), 2.5(a), and 2.5(b). This TLP system has a 100-ns pulse width and 10-ns rise time.

(a)

(b)

Fig. 2.4. (a) The TLP I-V curves of Tradition1, Tradition2, BFET1, and BFET2. (b) The zoomed-in view of (a) around the low-current region.

(a)

(b)

Fig. 2.5. (a) The TLP I-V curves of Modification1, Modification2, Modification3, and Modification4. (b) The zoomed-in view of (a) around the low-current region.

In Fig. 2.4(a), the TLP I-V curves can be simply discriminated between the main ESD clamp NMOS transistors with traditional or BFET layout styles. Although the second breakdown currents (It2) of these four designs can achieve over 6 A, the difference of on resistance (Ron) clearly distinguished the designs with traditional main ESD clamp NMOS transistor from those with BFET. Due to smaller total channel widths in Tradition1 and

Tradition2, their clamp voltage (Vclamp) and Ron are signification higher than those of BFET1 and BFET2. Higher Vclamp and Ron in Tradition1 and Tradition2 easily induced some damages to the internal circuits. In addition, the TLP I-V curves of Tradition1 and Tradition2 presented obvious two-stage Ron in Fig. 2.4(a). The phenomenon of two-stage Ron can be attributed to the changes of the discharging paths. The currents were conducted through the channel of the main ESD clamp NMOS transistor under the low current region, and they would be discharged by the parasitic npn bipolar transistor of the main ESD clamp NMOS transistor [18]. Moreover, the controlling circuits with 3-stage inverters can enhance the turn-on efficiency, such as lower trigger voltage (Vt1) and smaller on resistance, especially under the low current region in both traditional and BFET designs, as shown in Fig.

2.4(b). It was ever reported that the higher Vt1 and insufficient turn-on duration in the ESD devices will induce some damages to interface circuits [51]. The enhancement of the turn-on efficiency is more emphasized on the design with the controlling circuit of 3-stage inverter

2.4(b). It was ever reported that the higher Vt1 and insufficient turn-on duration in the ESD devices will induce some damages to interface circuits [51]. The enhancement of the turn-on efficiency is more emphasized on the design with the controlling circuit of 3-stage inverter