Unexpected Failure Spot in ND-mode ESD Stress

In Table 6.3 and Table 6.4, the lowest ESD robustness in the both AIO_4 designs is dominated by the ND-mode ESD stress. To identify the failure location for further improving its ESD level, the sample of AIO_4 after ND-mode ESD failure was de-layered. The unexpected ESD failure was located at the guard ring structure of the analog I/O pin with the pure-diode ESD protection design after ND-mode ESD stress, as shown in Figs. 6.10(a) and 6.10(b).

(a)

(b)

Fig. 6.10. (a) After 2.5-kV ND-mode ESD stress, the failure spot is located at the guard ring in AIO_4 of 1.8-V process. (b) The zoomed-in view of the failure spot at guard ring corner.

(a)

Pad Internal

circuits

ESD Cla m p S TFOD

Parasitic npn Bipolar

N+

PW N+/NW Guard Ring

VDD

VSS ND-mode

(b)

Fig. 6.11. (a) The parasitic npn bipolar transistor was constructed between the N+/PW diode and N+/NW guard ring. (b) The ESD current discharged through the parasitic npn bipolar transistor to grounded VDD during the ND-mode ESD stress causes the unexpected ESD failure.

Interaction between the N+/PW diode and the N+/NW guard ring was determined to be the cause of the failure under ND-mode ESD stress, in Fig. 6.10(b). In order to overcome latchup issues, the ESD protection devices are often surrounded by the guard rings, which are commonly connected to VDD or VSS. These guard rings could interact with the ESD protection devices to degrade the ESD robustness of the protection circuits [70]. As shown Fig. 3, the ND-mode ESD current should be discharged through the forward-biased diode between the I/O pad to VSS and the power-railESD clamp device to the grounded VDD.

However, the parasitic npn bipolar transistor which was formed between the N+/PW diode and the N+/NW guard ring was triggered on to form a direct discharging path between the I/O pad and the grounded VDD during the ND-mode ESD stress, as the dashed lines

illustrated in Fig. 6.11(a). In Fig. 6.11(b), it explains that the ND-mode ESD current is discharged through this parasitic bipolar transistor to cause damage at the corner of the guard ring due to the localized heat. In addition, the current gain (β) and the avalanche multiplication factor of the parasitic bipolar transistor are important parameters contributing to this failure mechanism. To overcome this failure, the spacing between N+/NW guard ring to N+/PW diode should be increased to eliminate the parasitic npn BJT effect. On the other hand, replacing the power-rail ESD clamp circuit with higher turn-on efficiency can avoid the turn-on of parasitic npn BJT to degrade the ESD robustness under ND-mode ESD stress. In addition, the power-rail ESD clamp circuit with high turn-on efficiency also can improve the ESD robustness of PS-mode ESD stress by providing the efficient and low-impedance discharging path between VDD and VSS. A successful modification with optimal power-rail ESD clamp circuit has been practically verified in a 0.13-μm CMOS process to achieve HBM ESD level of 7.0 kV for analog I/O cell.

6.3. Summary

Different ESD protection schemes for the analog input/output cells have been investigated to find the optimal analog ESD protection design for deep-submicron CMOS technology. According to the experimental results, the GGNMOS was not a suitable ESD protection device for analog I/O cells in deep-submicron CMOS process, such as 0.18-µm and below. The pure-diode ESD protection device between the pad to VDD (VSS) would be an optimal design for the analog I/O pins. In addition, the gate-driven NMOS for power-rail ESD clamp circuit also performs a higher ESD robustness for analog I/O pins in deep-submicron CMOS technology with STI structure. Finally, layout optimization with a wider spacing between N+/PW diode and N+/NW guard ring, as well as improvement on the power-rail ESD clamp circuit with higher turn-on efficiency, should be used to avoid the unexpected ESD failure under ND-mode ESD stress in such analog I/O cells.

Chapter 7

Active ESD Protection Design for Interface Circuits between Separated Power Domains against

Cross-Power-Domain ESD Stresses

In this chapter, a failure study of the internal ESD damage on the interface circuits of a 0.35-μm 3.3 V/5 V mixed-mode CMOS IC product with two separated power domains is presented [48]. The ESD failure spots were specially observed at the interface circuits of the separated power domains after negative-to-VDD mode (ND-mode) machine-model (MM) ESD stress [2] of 100 V. However, this IC product has a 2-kV human-body-model (HBM) ESD robustness [1] in each ESD test combination of I/O pin to power/ground pins. Therefore, the efficient ESD protection designs should be applied on the interface circuits between the separated power domains against such cross-power-domain ESD stresses. Secondly, several active cross-power-domain ESD protection designs were reviewed to compare their ESD protection strategies for interface circuits between separated power domains. Besides, one new active ESD protection design for the interface circuits between separated power domains has been also proposed to solve the interface circuit damages under cross-power-domain ESD stresses. This ESD protection design has been implemented by PMOS and NMOS transistors with the ESD-transient detection function in a 0.13-μm 1.2-V CMOS technology.

7.1. Failure Study under Cross-Power-Domain ESD Stresses

7.1.1. ESD Protection Cell Designs for the Commercial IC Product with Separated Power Pins

The ESD protection scheme for input, output, and power-rail ESD clamp circuits in this IC product is shown in Fig. 7.1. The internal circuit 1 is a digital circuit block, and the internal circuit 2 is an analog circuit block. Each circuit block has an individual power-rail ESD clamp circuit. The gate-grounded NMOS (GGNMOS) and gate-VDD PMOS

(GDPMOS) with a channel length/width of 0.8 μm/300 μm are used for pad-to-VSS and pad-to-VDD ESD protection at each I/O pad, respectively.

Fig. 7.1. ESD protection scheme in an IC product with separated power domains. The ESD protection circuits included input, output, and power-rail ESD clamp circuits.

The power-rail ESD clamp circuit, which is implemented with the substrate-triggered field-oxide-device (STFOD) [68], [71] with RC-based ESD transient detection circuit [6], [7]

is individually installed in each power domain, as illustrated in Fig. 7.1. The perimeter of the STFOD is equivalent to 216 μm. The STFOD as a power-rail ESD clamp circuit of a VDD (or VSS) cell had been successfully verified with over 4-kV HBM and 400-V MM ESD robustness in this 0.35-μm 3.3 V/5 V CMOS process. In addition, each I/O cell with GGNMOS and GDPMOS of 300-μm channel width also had been verified to achieve over 4-kV HBM and 400-V MM ESD robustness in the same process. Due to noise consideration between power domains, the VDD1 was separated from the VDD2. Then, the VSS1 and VSS2 only connected by the parasitic p-substrate resistance (Rsub) without bi-directional diode connection in this chip.

7.1.2. Internal ESD Damages on the Interface Circuits between Separated Power Domains

After HBM ESD tests of all I/O pins to each power/ground pin and power-to-ground

ESD test, the HBM ESD robustness achieved 2 kV, which is the basic specification for commercial IC products. However, the MM ESD robustness can not achieve 200 V in positive-to-VSS mode (PS-mode), positive-to-VDD mode (PD-mode), negative-to-VSS mode (NS-mode), and ND-mode MM ESD stresses. Even the ND-mode MM ESD robustness of Pin-A and Pin-B can not achieve 200 V by VDD1 and VDD2 shorting together in the test board under ND-mode ESD stress. The ESD test results for this IC product are shown in Table 7.1. After ESD tests are finished, a monitor on leakage current is used to judge whether the I/O pin under ESD test is passed or failed. The traced I-V characteristics of the investigated IC before and after ESD stress are shown in Fig. 7.2.

Table 7.1

HBM and MM ESD Robustness of the Pin-A and Pin-B I/O Pins in this IC Product

Fig. 7.2. After ND-mode MM ESD stress on I/O pins, the I-V characteristics of VDD2-to-VSS2 showed higher leakage currents than that before ESD stress.

Obviously, after the 200-V MM ESD stress, the leakage current at 3.3 V between VDD2 and VSS2 showed leakage current about 10 times higher, as compared with that of good dies.

From the measured I-V characteristics, there are some ESD damages in the internal circuits between VDD2 and VSS2 after ESD stress. These internal ESD damages have also been clearly observed by the physical failure analysis, such as emission microscope (EMMI) and scanning electron microscope (SEM).

7.1.3. Failure Mechanism under Cross-Power-Domain ESD Stresses

In order to indicate the failure locations caused by ND-mode MM ESD stresses, the EMMI was used to find abnormal ESD failure spots in this IC. The measured EMMI photos are shown in Figs. 7.3(a) and 7.3(b) with the corresponding IC layout patterns of the ND-mode MM ESD failure sample. All the circled areas in Fig. 7.3(c) are the ESD damage locations indicated by EMMI around the interface circuits after ND-mode MM ESD stress.

(a) (b)

(c)

Fig. 7.3. According to EMMI failure analysis, abnormal hot spots were found at the interface circuits (see the circled areas) after ND-mode MM ESD stress on (a) Pin-A, and (b) Pin-B. (c) The corresponding layout locations of the interface circuits were indicated the failure spots in (a) and (b).

The ESD damages are recognized at the interface circuits by comparison with circuits and layout patterns to the SEM photos of ESD damaged failure spots. After Pin-A ND-mode MM ESD stress, the SEM photos of failure spots are shown in Figs. 7.4(a) and 7.4(b). The clear failure spots were found in two PMOS transistors (M1 and M2) of the interface circuits.

(a) (b)

Fig. 7.4. After ND-mode MM ESD stress on Pin-A, the failure spots were located at (a) PMOS transistor (M1), and (b) the other PMOS transistor (M2).

Fig. 7.5. The ESD current could be discharged through the circuitous path to cause ESD damages to M1 and M2 during ND-mode MM ESD stress on Pin-A.

However, the Pin-A are connected to the internal circuit 1 through a 20-kΩ poly-resistor, which can effectively block the ESD currents to damage internal circuits nearby the I/O cell.

Therefore, the ESD current could be discharged by the circuitous path to cause damages on

the M1 and M2 after Pin-A ND-mode MM ESD stress, as shown in Fig. 7.5. Due to the larger device size of the Ma in Fig. 7.5, the ESD current didn’t destroy it during ND-mode MM ESD stress. On the other hand, the failure spots were also found in two transistors of interface circuits after Pin-B ND-mode MM ESD stress, as shown in Figs. 7.6(a) and 7.6(b). ND-mode MM ESD currents were discharged by two mainly current paths, as the dashed lines shown in Fig. 7.7. These two paths provided the current paths to distributive discharge ESD current.

The corresponding failure photos on the interface devices Mb and M3 are shown in Figs.

7.6(a) and 7.6(b), respectively.

(a) (b)

Fig. 7.6. (a) NMOS transistor (Mb), and (b) PMOS transistor (M3) of the interface circuits were destroyed after ND-mode MM ESD stress on Pin-B.

Fig. 7.7. ESD discharging paths during ND-mode MM ESD stress on Pin-B. The Mb and M3 were damaged after such ESD stress.

7.1.4. Proposed Solutions to Rescue such ESD Failures

To overcome such ESD failures at the interface circuits between separated power domains, adding the suitable blocking resistors (Rblock) to the interface devices and installing the bi-directional diode connection in original ESD protection scheme were proposed in Fig. 7.8. Two extra blocking resistors are added at the source terminal of the M1 and the gate terminal of the Mb, respectively. The bi-directional diode connection was used to connect the separated ground lines (VSS1 and VSS2). The diode numbers of the bi-directional diode connection were optimized to prevent different ground-line noise coupling issue between the separated ground lines of analog and digital circuit blocks. To further provide higher ground-line noise coupling isolation, the bi-directional silicon-controlled rectifier (SCR) [72] with ESD-detection circuit can be used to replace the bi-directional diode connection between the separated power lines (VDD1 and VDD2). By using the proposed ESD protection solutions, the ESD current will be effectively discharged along the desired connection of ground lines under ND-mode MM ESD stress. In addition, the blocking resistors also can avoid the ESD currents discharging through the undesirable paths. Therefore, the abnormal internal ESD damages can be overcome in this IC product with separated power lines.

Fig. 7.8. The proposed ESD protection solution to rescue ESD failures at the interface circuits of this IC product with separated power domains.

7.2. Active ESD Protection Designs for Interface Circuits between Separated Power Domains

7.2.1. ESD Threats and Damages of Interface Circuits between Separated Power Domains

With more circuit blocks integrated into an IC product to meet different applications, such circuit blocks usually have separated power domains to supply the power and ground signals in each individual circuit block. In addition, the interface circuits were also adopted to communicate with different circuit blocks inside the chip. However, the interface circuits between separated power domains are often damaged under cross-power-domain ESD stresses [33]-[38]. The bi-directional diode connections between the separated power domains are usually applied to construct a completely whole-chip ESD protection design [39], [40], as shown in Fig. 7.8. In general, the bi-directional diode connections are only used to connect the separated VSS pins due to different VDD1 and VDD2 voltage levels and noise-coupling considerations [39], [40]. When the ESD voltage was applied on the VDD1 and grounded VDD2 under the cross-power-domain ESD stresses, the ESD current can be discharged from the VDD1 to the VSS1 by the power-rail ESD clamp circuit 1 in the power domain one, from the VSS1 to the VSS2 through the inserted bi-directional diode connection, and then from the VSS2 to the grounded VDD2 through the other power-rail ESD clamp circuit 2 in the power domain two, as the discharged path shown by dashed line in Fig. 7.9(a). The Vh1 and Vh2 are the holding voltage of the power-rail ESD clamp circuits 1 and 2, respectively. Then, the Vhd is the holding voltage of the bi-directional diode connection between the separated power domains. Among the parameters, the R1, R2, and Rd are the turn-on resistances of the power-rail ESD clamp circuits 1, 2, and the bi-directional diode connection, respectively.

When the ESD current was conducted by this long discharging path, it would induce the overstress voltage across the each MOS transistor in interface circuits between separated power domains [40]-[42]. The induced voltage drops with discharging ESD currents from VDD1 to VDD2 on each node of the interface circuit had been estimated, as shown in Fig.

7.9(a). The voltage potential at node A could be raised up to the VDD1 because the driver’s PMOS transistor (Mp1) had an initially floating gate situation. The highest voltage drop was applied across the gate oxide of the receiver’s PMOS transistor (Mp2) in interface circuits under the VDD1 to VDD2 ESD stresses. On the other hand, the highest voltage drop was also generated across the gate oxide of the receiver’s NMOS transistor (Mn2) in interface circuits

under the VDD1 to VSS2 ESD stresses. The similar estimation on voltage drops during ESD stress was presented in Fig. 7.9(b).

(a)

(b)

Fig. 7.9. The estimations of the induced voltage potential under the cross-power-domain (a) VDD1-to-VDD2, and (b) VDD1-to-VSS2, ESD stresses.

Therefore, the 2^nd ESD clamp designs were usually installed nearby the MOS transistors of receiver to reduce the overstress voltage under the cross-power-domain ESD stresses

[40]-[42], as shown in Figs. 7.9(a) and 7.9(b). As the CMOS technologies being continually shrunk toward nanometer scales, the breakdown voltages of ultra-thin gate oxide in the MOS transistors were sharply reduced to impact the ESD protection designs. It was important to avoid the gate oxide damages of the MOS transistors in the interface circuits by ESD-current induced overstress voltages. The overview on some 2^nd ESD clamp designs will be presented and compared in the following sub-section.

7.2.2. Review on ESD Protection Designs for Interface Circuits between Separated Power Domains

The resistor-diode clamp design [40], which consists of a resistor (R1) and two diodes, was allocated in the interface circuits between separated power domains in order to restrict the ESD current distribution and to clamp the overstress voltage across the gate oxide of the receiver’s MOS transistors, as shown in Fig. 7.10.

Fig. 7.10. The ESD protection design with resistor-diode clamp had been proposed to protect the interface circuits between separated power domains [40].

These two clamped diodes can be respectively replaced by the gate-grounded NMOS (GGNMOS) transistor and gate-VDD PMOS (GDPMOS) transistor to further enhance the clamping efficiency. However, such traditional junction-breakdown clamp designs with diodes, GGNMOS, or GDPMOS could not be suitable for interface circuits with ultra-thin oxide against cross-power-domain ESD stresses. Therefore, some second ESD protection

designs with special trigger mechanisms, such as the modified interface circuits with special drivers and receivers [41] as well as the ground-current-trigger (GCT) NMOS transistor [42], had been proposed to efficiently reduce the overstress voltages across the ultra-thin gate oxides of the MOS transistors in interface circuits between separated power domains.

(a)

(b)

Fig. 7.11. The ESD protection design with (a) a special driver and (b) a special receiver for interface circuits between separated power domains [41].

The special driver and receiver had been implemented for interface circuits between separated power domains, which were collaborated with an ESD detector to accomplish

differently desired functions under the cross-power-domain ESD stress condition and the normal circuit operation condition, as presented in Figs. 7.11(a) and 7.11(b) [41]. The special driver was composed of a 1-stage NAND gate and a 1-stage inverter. Through different signals from the ESD detector, the driver can be respectively performed as cascaded 2-stage inverters and a biased-high 1-stage inverter under normal circuit operation condition and VDD1-to-VDD-2 cross-power-domain ESD stress, as illustrated in Fig. 7.11(a). In addition, the special receiver consisted of a 1-stage inverter, a PMOS transistor (Mp3) cascoded on the inverter, and a NMOS transistor (Mn3) in parallel to the inverter. The cascoded PMOS and the parallel NMOS transistors, both of which were controlled by the ESD detector, will be respectively turned on and off under normal circuit operation condition, whereas the Mp3 and the Mn3 will be respectively turned off and on under cross-power-domain ESD stress, as shown in Fig. 7.11(b). Although such special designs in the driver and receiver [41] can reduce and restrain the overstress voltage across the gate oxide of receiver’s PMOS and NMOS transistors, the complicated connection could be an obstacle to practical applications.

Fig. 7.12. The ESD protection design with grounded-current-trigger (GCT) NMOS transistor for interface circuits between separated power domains [42].

On the other hand, the grounded-current-trigger (GCT) NMOS transistor [42] had been also proposed to act as a 2^nd ESD clamp for interface circuits between separated power domains, as shown in Fig. 7.12. The GCT NMOS transistor can be turned on to clamp the overstress voltage across the gate oxide of receiver’s PMOS and NMOS transistors by the

induced voltage drop between VSS1 and VSS2 under cross-power-domain ESD stress. But, it will be kept off due to the same voltage potential on VSS1 and VSS2 under normal circuit operation condition. This active 2^nd ESD clamp design can achieve high ESD robustness under cross-power-domain ESD stress [42]. In this work, one new active ESD protection design for interface circuits between separated power domains was proposed to solve this problem.

7.3. New Cross-Power-Domain ESD Protection Design

7.3.1. Implementation of the New Proposed Design for Cross-Power-Domain ESD Protection

An ESD protection design was implemented by gate-controlled PMOS (GC-PMOS) and

An ESD protection design was implemented by gate-controlled PMOS (GC-PMOS) and