Realization of Power-Rail ESD Clamp Circuit

3.2.1. New Proposed ESD-transient Detection Circuit

Area-efficient ESD-transient detection circuit with ultra small capacitor has been presented in Fig. 3.2, which adopts capacitance coupling mechanism to achieve the required functions on the power-rail ESD clamp circuit. This area-efficient ESD-transient detection circuit consists of an ultra small capacitor (C1), cascode NMOS transistors (Mnc1 and Mnc2), a resistor (R1), and a switch NMOS transistor (Mns), commanding the main ESD clamp NMOS transistor through a controlling circuit with single-stage inverter. The ultra small capacitor is implemented by metal-oxide-metal (MOM) parasitic capacitance. The cascode NMOS transistors are used as a large resistor and cooperated with the ultra small capacitor to construct a capacitance coupling network [60], [61]. The node A between the ultra small capacitor and the cascode NMOS transistors is connected to gate terminal of the switch NMOS transistor. Then, its drain terminal is tied to the VDD through the resistor and also connected to the input of the controlling circuit.

Fig. 3.2. Novel power-rail ESD clamp circuit with an new proposed ESD-transient detection circuit.

This new proposed ESD-transient detection circuit is composed of an ultra small capacitor (C1), cascode NMOS transistors (Mnc1 and Mnc2), a resistor (R1), and a switch NMOS transistor (Mns).

Through the controlling circuit, the switch NMOS transistor can rule the main ESD clamp NMOS transistor to keep at “on” or “off” state. Finally, the main ESD clamp NMOS transistor has been drawn with the BigFET layout style, which has the minimum drain-contact-to-poly -gate spacing of 0.25 μm and without silicide blocking on its diffusion.

This testchip is fabricated in a 130-nm 1.2-V CMOS process. Compared with the layout area of the power-rail ESD clamp circuit with traditional RC-based ESD-transient detection circuit, this work with the new proposed ESD-transient detection circuit is far smaller in the power-rail ESD clamp circuit, as shown in Figs. 3.3(a) and 3.3(b). The cell height of the novel power-rail ESD clamp circuit is reduced about 15 % and the layout area of the ESD-transient detection circuit is more reduced about 50 %.

(a)

(b)

Fig. 3.3. The comparison of the layout areas between the power-rail ESD clamp circuits with (a) the traditional, and (b) the new proposed, ESD-transient detection circuits.

3.2.2. Operation Principles

During the positive VDD-to-VSS ESD stress condition, the potential of the node A will be synchronously evaluated toward a positive voltage potential by the capacitance coupling of the ultra small capacitor to trigger on the switch NMOS transistor. Then, through the switch NMOS transistor and the controlling circuit, the gate terminal of the main ESD clamp NMOS transistor will be promptly charged toward the positive voltage potential. The main ESD clamp NMOS transistor is turned on to clamp and discharge the huge ESD voltage and

ESD current. The turn-on duration of the main ESD clamp NMOS transistor is dominated by the potential of node A. This potential is synchronously kept at the positive voltage potential by the capacitance coupling; however, it will be slowly pulled down due to the turned-on cascode NMOS transistors. Because the gate terminals of these two cascode NMOS transistors with small device dimensions have been connected to their drain terminals, they are operated at saturation region to provide a huge resistance under the positive VDD-to-VSS ESD event. Finally, when the potential of node A is lower than the threshold voltage of NMOS transistor, the switch NMOS transistor will be turned off to force the main ESD clamp NMOS transistor off. Based on the simulation result, the turn-on duration of the main ESD clamp NMOS transistor can achieve over 600 ns in the power-rail ESD clamp circuit with the ultra small capacitor of only ~10 femto-Farad (fF), as presented in Fig. 3.4.

Fig. 3.4. The simulation result of the voltage potential on the gate terminal of main ESD clamp NMOS transistor in power-rail ESD clamp circuit.

The 3-V voltage pulse with rise time of 2 ns was applied on VDD node with VSS node grounded. The voltage potential on the gate terminal of main ESD clamp NMOS transistor is higher than the threshold voltage of ~0.35 V during the period of ~620 ns. The detailed design parameters, such as device sizes of cascode NMOS transistors and switch NMOS transistor, have been listed in Table 3.1. On the other hand, the parasitic drain-bulk diode of the main ESD clamp NMOS transistor can provide low impedance path under negative VDD-to-VSS ESD stress. Under the normal power-on condition, the normal VDD power-on voltage waveform has a rise time in the order of milli-second (ms). Such power-on voltage waveform will not produce enough coupling potential on the node A to trigger on the switch NMOS transistor. The potential of node A will be actually kept at ground through the high

resistance path of the cascode NMOS transistors. Therefore, the main ESD clamp NMOS transistor will be kept at “off” state under the normal circuit operation condition. Besides, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit also presents a high immunity against mis-trigger and latch-on event.

Table 3.1

Design Parameters in the Power-Rail ESD Clamp Circuit with the New Proposed ESD-Transient Detection Circuit