Summary

The designs with controlling circuits of 3-stage inverters and 1-stage inverter have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.

In addition, the circuit performance among the four different main ESD clamp NMOS transistors drawn with different drain-contact-to-poly-gate spacings and co-designed with different inverter stages in the controlling circuits are compared. According to the experiments and analyses, the 3-stage inverters for controlling circuit and BFET layout style for the main ESD clamp NMOS transistor can slightly increase the ESD robustness, but they will dramatically degrade the immunity against mis-trigger and latch-on issues under the EFT test and fast power-on condition. The 1-stage inverter should be an appropriate and reliable candidate for the controlling circuit in the power-rail ESD clamp circuits. Finally, the latch-on phenomenon has been successfully observed by the emission microscope with InGaAs FPA detector. The root cause to induce such failure can be attributed to the abnormal mechanism of the voltage drop across the n-well resistance after the EFT test.

Chapter 3

Area-Efficient ESD-Transient Detection Circuit with Ultra Small Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

In this chapter, an efficient ESD-transient detection circuit has been proposed and verified in 130-nm 1.2-V CMOS technology. This design abandons the feedback circuit techniques and adopts capacitance coupling mechanism to accomplish the desirable function on commanding the main ESD clamp NMOS transistor. Through experimental measurements, such as turn-on verification, transmission line pulse (TLP) stress [50], ESD stress, and fast power-on test, this power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit presents an excellent performance to meet the specified requirements.

According to the measured results, the new proposed ESD-transient detection circuit possesses the sufficient turn-on duration under the ESD-stress conditions and high mis-trigger and latch-on immunities under the fast power-on conditions.

3.1. Background

In order to efficiently protect the core circuits realized with much thinner gate oxide in nanoscale CMOS technology, some previous studies had reported the efficient NMOS-based power-rail ESD clamp circuits without snapback operation [8]-[11], [17]-[19], [58], [59]. All of them adopted the gate-driven mechanism, which was basically implemented by an ESD-transient detection circuit and a controlling circuit, to respectively command the main ESD clamp NMOS transistor into the on state or the off state under the ESD-stress conditions and normal circuit operation conditions, as illustrated in Fig. 3.1. Two major different circuit schemes, which are RC-time delay technique [6]-[11] and capacitance coupling mechanism [18], [19], were usually used as the ESD-transient detection circuit in the power-rail ESD clamp circuit. Then, the controlling circuit was always implemented by single- or multi-stage inverters. In such power-rail ESD clamp circuit, main ESD clamp NMOS transistor can

thoroughly discharge huge ESD current by its channel current to exhibit excellent turn-on efficiency, such as lower trigger voltage (Vt1) and lower clamped voltage (Vclamp).

Fig. 3.1. Typical design scheme for NMOS-based power-rail ESD clamp circuit with an ESD-transient detection stage and controlling stage.

The main ESD clamp NMOS transistor without snapback operation has to be kept at the on state under the whole duration of ESD events in order to ensure that the ESD current can be discharged by its channel current. Based on the traditional RC-based ESD-transient detection circuit [6], [7], the RC-time constant which is the product of the resistance (R) and capacitance (C) essentially dominated the turn-on duration of the main ESD clamp NMOS transistor. Therefore, the RC-time constant of the RC-based ESD-transient detection circuit should be designed to sufficiently achieve a desirable turned-on duration of the main ESD clamp NMOS transistor. In general, the turn-on duration was adjusted to meet the period of human-body-model (HBM) ESD event, which is about several hundred nano-seconds (ns) [1].

The extended RC-time constant not only accompanies with the larger layout sizes of the resistance and capacitance, but also is subject to mis-trigger the main ESD clamp NMOS transistor under fast power-on applications [10]. Several previous works proposed special circuit schemes with feedback circuit techniques to extend the turn-on duration under a small RC-time constant [9], [10], [17]-[19]. However, those feedback circuit designs always suffered from the latch-on threats under the fast power-on events or the electrical fast transient noise [20], [21]. Besides, other circuit schemes without feedback circuit techniques, such as on-time control circuit [9] and multi-RC-triggered [11], also had been presented to achieve the desirable turn-on duration and to avoid the latch-on threat. However, extra resistors and capacitors have to be implanted into these designs, which occupying a quite

silicon area. In this chapter, an efficient ESD-transient detection circuit adopted capacitance coupling mechanism is proposed to accomplish the desirable function with ultra-small capacitance for using in power-rail ESD clamp circuit.

3.2. Realization of Power-Rail ESD Clamp Circuit

3.2.1. New Proposed ESD-transient Detection Circuit

Area-efficient ESD-transient detection circuit with ultra small capacitor has been presented in Fig. 3.2, which adopts capacitance coupling mechanism to achieve the required functions on the power-rail ESD clamp circuit. This area-efficient ESD-transient detection circuit consists of an ultra small capacitor (C1), cascode NMOS transistors (Mnc1 and Mnc2), a resistor (R1), and a switch NMOS transistor (Mns), commanding the main ESD clamp NMOS transistor through a controlling circuit with single-stage inverter. The ultra small capacitor is implemented by metal-oxide-metal (MOM) parasitic capacitance. The cascode NMOS transistors are used as a large resistor and cooperated with the ultra small capacitor to construct a capacitance coupling network [60], [61]. The node A between the ultra small capacitor and the cascode NMOS transistors is connected to gate terminal of the switch NMOS transistor. Then, its drain terminal is tied to the VDD through the resistor and also connected to the input of the controlling circuit.

Fig. 3.2. Novel power-rail ESD clamp circuit with an new proposed ESD-transient detection circuit.

This new proposed ESD-transient detection circuit is composed of an ultra small capacitor (C1), cascode NMOS transistors (Mnc1 and Mnc2), a resistor (R1), and a switch NMOS transistor (Mns).

Through the controlling circuit, the switch NMOS transistor can rule the main ESD clamp NMOS transistor to keep at “on” or “off” state. Finally, the main ESD clamp NMOS transistor has been drawn with the BigFET layout style, which has the minimum drain-contact-to-poly -gate spacing of 0.25 μm and without silicide blocking on its diffusion.

This testchip is fabricated in a 130-nm 1.2-V CMOS process. Compared with the layout area of the power-rail ESD clamp circuit with traditional RC-based ESD-transient detection circuit, this work with the new proposed ESD-transient detection circuit is far smaller in the power-rail ESD clamp circuit, as shown in Figs. 3.3(a) and 3.3(b). The cell height of the novel power-rail ESD clamp circuit is reduced about 15 % and the layout area of the ESD-transient detection circuit is more reduced about 50 %.

(a)

(b)

Fig. 3.3. The comparison of the layout areas between the power-rail ESD clamp circuits with (a) the traditional, and (b) the new proposed, ESD-transient detection circuits.

3.2.2. Operation Principles

During the positive VDD-to-VSS ESD stress condition, the potential of the node A will be synchronously evaluated toward a positive voltage potential by the capacitance coupling of the ultra small capacitor to trigger on the switch NMOS transistor. Then, through the switch NMOS transistor and the controlling circuit, the gate terminal of the main ESD clamp NMOS transistor will be promptly charged toward the positive voltage potential. The main ESD clamp NMOS transistor is turned on to clamp and discharge the huge ESD voltage and

ESD current. The turn-on duration of the main ESD clamp NMOS transistor is dominated by the potential of node A. This potential is synchronously kept at the positive voltage potential by the capacitance coupling; however, it will be slowly pulled down due to the turned-on cascode NMOS transistors. Because the gate terminals of these two cascode NMOS transistors with small device dimensions have been connected to their drain terminals, they are operated at saturation region to provide a huge resistance under the positive VDD-to-VSS ESD event. Finally, when the potential of node A is lower than the threshold voltage of NMOS transistor, the switch NMOS transistor will be turned off to force the main ESD clamp NMOS transistor off. Based on the simulation result, the turn-on duration of the main ESD clamp NMOS transistor can achieve over 600 ns in the power-rail ESD clamp circuit with the ultra small capacitor of only ~10 femto-Farad (fF), as presented in Fig. 3.4.

Fig. 3.4. The simulation result of the voltage potential on the gate terminal of main ESD clamp NMOS transistor in power-rail ESD clamp circuit.

The 3-V voltage pulse with rise time of 2 ns was applied on VDD node with VSS node grounded. The voltage potential on the gate terminal of main ESD clamp NMOS transistor is higher than the threshold voltage of ~0.35 V during the period of ~620 ns. The detailed design parameters, such as device sizes of cascode NMOS transistors and switch NMOS transistor, have been listed in Table 3.1. On the other hand, the parasitic drain-bulk diode of the main ESD clamp NMOS transistor can provide low impedance path under negative VDD-to-VSS ESD stress. Under the normal power-on condition, the normal VDD power-on voltage waveform has a rise time in the order of milli-second (ms). Such power-on voltage waveform will not produce enough coupling potential on the node A to trigger on the switch NMOS transistor. The potential of node A will be actually kept at ground through the high

resistance path of the cascode NMOS transistors. Therefore, the main ESD clamp NMOS transistor will be kept at “off” state under the normal circuit operation condition. Besides, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit also presents a high immunity against mis-trigger and latch-on event.

Table 3.1

Design Parameters in the Power-Rail ESD Clamp Circuit with the New Proposed ESD-Transient Detection Circuit

3.3. Experimental Results

3.3.1. Turn-On Verification under ESD-Like Stress Condition

In order to observe the turn-on efficiency of the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit, 2.4-V and 5-V ESD-like voltage pulses with 2-nano-seconds (ns) rise time are applied on the VDD terminal with VSS terminal grounded.

The voltage pulses with a rise time of 2 ns and duration of 1 μs generated from a pulse generator are used to simulate the fast rising edge of HBM ESD event [12]. The sharp-rising edge of the ESD-like voltage pulse will be detected by the ESD-transient detection circuit and then to turn on the switch NMOS transistor. The main ESD clamp NMOS transistor is therefore triggered on by the controlling circuit. When the main ESD clamp NMOS transistor is turned on, the voltage waveform on VDD terminal will be clamped as the measured results shown in Fig. 3.5. According to the measured results in Fig. 3.5, the new proposed design exhibits an excellent turn-on efficiency to clamp the overshooting voltage to a much lower voltage level. The voltage waveform of the new proposed design can be constantly clamped by the turned-on main ESD clamp NMOS transistor during the whole 1-μs pulse width. On the contrary, the voltage waveform of the traditional design will quickly raise and its clamped voltage is much higher than that of the new proposed design after the duration of 200 ns. The

new proposed ESD-transient detection circuit can efficiently extend the turn-on duration of the main ESD clamp NMOS transistor in the power-rail ESD clamp circuit. The longer turn-on duration of the main ESD clamp NMOS transistor would assure that the low impedance path was entirely provided from VDD to VSS under the whole HBM ESD event, and would also enhance the ESD robustness of the power-rail ESD clamp circuit.

Fig. 3.5. The measured voltage waveforms of power-rail ESD clamp circuits with the traditional and new proposed ESD-transient detection circuits under 5-V ESD-like voltage pulses with 2-ns rise time.

3.3.2. TLP I-V Characteristics and ESD Robustness

The Transmission Line Pulse (TLP) [17] measured I-V characteristics of the power-rail ESD clamp circuits with the traditional and new proposed ESD-transient detection circuits are shown in Fig. 3.6. This TLP system has a 100-ns pulse width and 2-ns rise time. These two power-rail ESD clamp circuits present the desired TLP I-V characteristics. No obvious difference among the TLP measured results was observed between these two designs. The second breakdown currents (It2) of these two power-rail ESD clamp circuits can achieve over 7 A. Their clamped voltages (Vclamp) and on resistances (Ron) are similar. Table 3.2 shows the HBM and MM ESD robustness of these two power-rail ESD clamp circuits. The HBM and MM ESD robustness of the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit are 8.0 kV and 400 V, respectively, which are obviously higher than those of the power-rail ESD clamp circuit with the traditional ESD-transient detection circuit. According to the failure analysis by SEM observation, the failure spot of the traditional design is located on the unexpected junction melting damages between the n+/n-well minority guard ring and the p+ majority guard ring after 6.0-kV HBM ESD stress, as shown in Figs. 3.7(a) and 3.7(b). Because the power-rail ESD clamp circuit with

traditional ESD-transient detection circuit has insufficient turn-on duration, the huge ESD current could not efficiently discharge during the whole HBM ESD event to induce the unexpected failure spot after 6.0-kV HBM ESD stress.

Fig. 3.6. The TLP I-V curves of the power-rail ESD clamp circuits with the traditional and the new proposed ESD-transient detection circuits.

Table 3.2

HBM and MM ESD Robustness of the Power-Rail ESD Clamp Circuits with the Traditional and the New Proposed ESD-Transient Detection Circuits

(a) (b)

Fig. 3.7. (a) The failure spot of the power-rail ESD clamp circuit with the traditional ESD-transient detection circuit after 6.0-kV HBM ESD stresses. (b) Zoomed-in view of failure spot at Location A.

3.3.3. Fast Power-On Condition and Discussion

In general, the normal VDD power-on voltage waveform has a rise time in the order of milli-second (ms) and amplitude of VDD operation voltage. Due to such a slow rise time and small amplitude in normal power-on conditions, the coupling potential on the node A is too weak to turn on the switch NMOS transistor. Therefore, the main ESD clamp NMOS transistor will be well kept at off state. In this work, both power-rail ESD clamp circuits with the traditional and the new proposed ESD-transient detection circuits can successfully achieve this desirable task under normal power-on conditions. However, some previous studies [9]-[11], [20], [21] have illustrated that several power-rail ESD clamp circuits with RC-based ESD-transient detection circuits and feedback circuit schemes were easily mis-triggered and into the latch-on state under the fast power-on conditions with the rise time in the order of nano-second (ns). The design with the new proposed ESD-transient detection circuit has been applied with 1.2-V voltage pulses with 100-ns or 2-ns rise time, both of which are used to simulate the fast power-on condition, to investigate its immunities against the mis-trigger and latch-on event. The measured results are respectively shown in Figs. 3.8(a) and 3.8(b). Its measured voltage waveforms do not show any obvious degradation under the fast power-on condition with voltage pulse of 1.2 V and rise time of 100 ns or 2 ns. On the contrary, the power-rail ESD clamp circuit with the traditional ESD-transient detection circuit suffered from the mis-trigger under the fast power-on conditions. Its voltage waveforms will be slightly degraded under the 1.2-V fast power-on pulse with 100-ns rise time, and be dramatically degraded under that with 2-ns rise time. Since the feedback circuit schemes were not used in this work, the latch-on event was not observed in these two power-rail ESD clamp circuits. Compared with the results in the previous studies [9]-[11], [18], [19], the power-rail ESD clamp circuit with new proposed ESD-transient detection circuit possesses an excellent immunity against mis-trigger and latch-on event. Because the new proposed ESD-transient detection circuit adopts the capacitance coupling mechanism, this new proposed design not only distinguishes the abnormal overshooting voltage pulse by its rise time, but also discriminates this voltage pulse by its voltage amplitude. The new proposed ESD-transient detection circuit can easily distinguish the ESD event from the fast power-on condition with the voltage amplitude of 1.2 V and the rise time of 2 ns.

In addition, the electrical fast transient (EFT) test [52] is applied on the power-rail ESD clamp circuit with new proposed ESD-transient detection circuit to judge its immunity against fast transient noise on the power line. With 10-V EFT voltage stress on the VDD node,

the measured result is shown in Fig. 3.9. The new proposed design can efficiently clamp the overshooting voltage pulse on VDD node during EFT stress. After the duration of 10-V EFT voltage pulse, the voltage potential on VDD node is well remained at 1.2 V and no conducting current from VDD to VSS is observed. According to the EFT measured result, the new proposed ESD-transient detection circuit also possesses an excellent immunity against mis-trigger and latch-on event under electrical fast transient noise applied on VDD terminal.

(a) (b)

Fig. 3.8. The measured voltage waveforms of the power-rail ESD clamp circuits with the traditional and the new proposed ESD-transient detection circuits under the 1.2-V fast power-on conditions with (a) 100-ns rise time and (b) 2-ns rise time.

Fig. 3.9. Under the 10-V EFT voltage pulse, the measured voltage waveform of the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit.

3.4. Summary

A new proposed ESD-transient detection circuit cooperated with NMOS-based power-rail ESD clamp circuit has been presented and successfully verified in a 130-nm CMOS technology. The new proposed ESD-transient detection circuit adopts the capacitance coupling mechanism and a switch NMOS transistor to command the main ESD clamp NMOS transistor by the general controlling circuit with single-stage inverter. According to the measured results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit exhibits the superior ESD robustness of 8.0 kV and 400 V in HBM and MM ESD stresses, respectively. Moreover, it also possesses an excellent immunity against the mis-trigger and latch-on event under the 1.2-V fast power-on condition with the rise time of 2 ns.

Chapter 4

Implementation of Initial-On ESD Protection Concept with PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

In this chapter, a novel initial-on SCR design is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on SCR design is realized by circuit skill with the PMOS transistor in general CMOS processes

In this chapter, a novel initial-on SCR design is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on SCR design is realized by circuit skill with the PMOS transistor in general CMOS processes