Controlling Circuits and Layout Styles

Both controlling circuits, which are the 1-stage inverter and the 3-stage inverters, are respectively arranged to command the main ESD clamp NMOS transistors with different drain-contact-to-poly-gate spacings. One of the main ESD clamp NMOS transistors has the layout style with minimized drain-contact-to-poly-gate spacing (D) and no silicide blocking (SB) on its diffusion, as shown in Fig. 2.1(a). This NMOS transistor, which is the Big FET (BFET), will be expected to have no snapback operation. However, another one has a totally different layout style with extended drain-contact-to-poly-gate spacing (D) and silicide blocking (SB) on its diffusion, as shown in Fig. 2.1(b). It is a traditional ESD clamp NMOS transistor with snapback operation. It has been proven that the parasitic npn bipolar transistor was turned on to induce the snapback operation in such ESD clamp NMOS transistor [4], [5].

The drain-contact-to-poly-gate spacings of the BFET and traditional ESD clamp NMOS

transistors are 0.25 μm and 2.0 μm, respectively. Besides, different layouts on the main ESD clamp NMOS transistor, called the modification design in this work, with a drain-contact-to-poly-gate spacing of 0.75 μm has been also implemented in the testchip with or without silicide blocking on its drain-side diffusion. Through such splits in layout, the influences of the drain-side equivalent resistance on circuit performance and ESD robustness can be used to judge the optimal layout style for the main ESD clamp NMOS transistor.

(a)

(b)

Fig. 2.1. The main ESD clamp NMOS transistor has (a) the BFET layout style with the drain-contact-to-poly-gate spacing (D) of 0.25 μm and no silicide blocking (SB) on its diffusions, and (b) the traditional layout style with the D of 2.0 μm and SB on its drain-side diffusions.

The eight designs of power-rail ESD clamp circuits from the combinations of the main ESD clamp NMOS transistor in different layout styles and the controlling circuit with different inverter stages have been drawn in the testchip for comparison, as shown in Table 2.1. For comparison purpose, the layout areas of the main ESD clamp NMOS transistors among those eight designs are kept the same in layout. Therefore, the total channel width of the traditional ESD clamp NMOS transistor is 624 μm, whereas that of the BFET is about 2600 μm. The total channel width of main ESD clamp NMOS transistor with the drain-contact-to-poly-gate spacing of 0.75 μm is 1144 μm. In addition, the RC time constant in those eight designs are all kept at 200 ns. This testchip has been fabricated in a 0.13-μm 1.2-V CMOS process.

Table 2.1

Eight Designs of the Power-Rail ESD Clamp Circuits Verified in this Work

2.2. Experimental Results in Component-Level Tests

2.2.1. DC Leakage Current

Power-rail ESD clamp circuits must be kept off to avoid unnecessary VDD-to-VSS leakage current under normal circuit operation conditions. However, the main ESD clamp

NMOS transistors always have huge device dimension to achieve the required ESD robustness. Thus, they will be some concern on leakage, especially in the nanoscale CMOS technology. The leakage currents of the power-rail ESD clamp circuits with controlling circuits of 1-stage inverter and 3-stage inverters in are shown in Figs. 2.2(a) and 2.2(b), respectively.

(a)

(b)

Fig. 2.2. DC leakage currents among the power-rail ESD clamp circuits of different designs with controlling circuit of (a) with 1-stage inverter and (b) 3-stage inverters.

There is no obvious difference on the leakage currents between the power-rail ESD clamp circuits with different controlling circuits under the identical main ESD clamp NMOS transistor. The leakage currents of BFET1 (or BFET2) are 0.5 μA under the VDD bias of 1.2 V, whereas those of Tradition1 (or Tradition2) are below 0.15 μA at the same VDD bias. In addition, no significant difference of the leakage currents is observed between the main ESD clamp NMOS transistor with or without silicide blocking (SB) on its diffusion, as illustrated in the measured results of Modification1 and Modification2 (or Modification3 and Modification4). According to the measured results, the leakage currents of Tradition1 and Trdition2 are 3-times less than those of BFET1 and BFET2 due to the large channel widths in BFET1 and BFET2. Therefore, the leakage current of the power-rail ESD clamp circuit is strongly dependent on the channel width of the main ESD clamp NMOS transistor.

2.2.2. Turn-On Verification under ESD-Like Stress Condition

To observe the turn-on efficiency among the different power-rail ESD clamp circuits, a 2.4-V ESD-like voltage pulse with 2-nano-seconds (ns) rise time is applied on the VDD terminal with VSS terminal grounded in each circuit. The voltage pulse with a rise time of 2 ns and duration of 600 ns generated from a pulse generator is used to simulate the fast rising edge of HBM ESD event [1]. The sharp-rising edge of the ESD-like voltage pulse will be detected by the RC-based ESD-transient detection circuit and then to turn on the main ESD clamp NMOS transistor. When the main ESD clamp NMOS is turned on, the voltage waveform on VDD node will be clamped as the measured results shown in Figs. 2.3(a) and 2.3(b). Tradition1 and BFET1, both of which have 1-stage inverter in the controlling circuits, presented similar voltage waveforms under 2.4-V ESD-like voltage pulses. Besides, Tradition2 clamped the overshoot voltage pulses to a lower voltage level during the first 300 ns of the ESD-like voltage pulses. However, the BFET2 performs an excellent ability to clamp the overshoot voltage pulse to a much lower voltage level, as shown in Fig. 2.3(a). On the other hand, the influences of drain-side silicide blacking on turn-on behaviors of the power-rail ESD clamp circuits have been measured in Fig. 2.3(b). Under the same drain-contact-to-poly-gate spacings of 0.75 μm, Modification3 exhibits the best turn-on efficiency among other designs. Besides, the turn-on efficiency of Modification4 is higher than that of Modification1 and Modification2 during the first 350-ns pulse duration.

According to the measured results, the controlling circuit with 3-stage inverters seems to be an optimal candidate to implement the main ESD clamp NMOS transistor with BFET layout

style in the power-rail ESD clamp circuit. The controlling circuit would hold a dominant factor on the turn-on behaviors of the power-rail ESD clamp circuit.

(a)

(b)

Fig. 2.3. The measured voltage waveforms of (a) Tradition1, Tradition2, BFET1, and BFET4, and of (b) Modification1, Modification2, Modification3, and Modification4, under 2.4-V ESD-like voltage pulses with 2-ns rise time.

2.2.3. TLP I-V Characteristics and HBM ESD Robustness

The Transmission Line Pulse (TLP) [50] measured I-V characteristics of the power-rail ESD clamp circuits are shown in Figs. 2.4(a), 2.4(b), 2.5(a), and 2.5(b). This TLP system has a 100-ns pulse width and 10-ns rise time.

(a)

(b)

Fig. 2.4. (a) The TLP I-V curves of Tradition1, Tradition2, BFET1, and BFET2. (b) The zoomed-in view of (a) around the low-current region.

(a)

(b)

Fig. 2.5. (a) The TLP I-V curves of Modification1, Modification2, Modification3, and Modification4. (b) The zoomed-in view of (a) around the low-current region.

In Fig. 2.4(a), the TLP I-V curves can be simply discriminated between the main ESD clamp NMOS transistors with traditional or BFET layout styles. Although the second breakdown currents (It2) of these four designs can achieve over 6 A, the difference of on resistance (Ron) clearly distinguished the designs with traditional main ESD clamp NMOS transistor from those with BFET. Due to smaller total channel widths in Tradition1 and

Tradition2, their clamp voltage (Vclamp) and Ron are signification higher than those of BFET1 and BFET2. Higher Vclamp and Ron in Tradition1 and Tradition2 easily induced some damages to the internal circuits. In addition, the TLP I-V curves of Tradition1 and Tradition2 presented obvious two-stage Ron in Fig. 2.4(a). The phenomenon of two-stage Ron can be attributed to the changes of the discharging paths. The currents were conducted through the channel of the main ESD clamp NMOS transistor under the low current region, and they would be discharged by the parasitic npn bipolar transistor of the main ESD clamp NMOS transistor [18]. Moreover, the controlling circuits with 3-stage inverters can enhance the turn-on efficiency, such as lower trigger voltage (Vt1) and smaller on resistance, especially under the low current region in both traditional and BFET designs, as shown in Fig.

2.4(b). It was ever reported that the higher Vt1 and insufficient turn-on duration in the ESD devices will induce some damages to interface circuits [51]. The enhancement of the turn-on efficiency is more emphasized on the design with the controlling circuit of 3-stage inverter cooperated with BFET. However, the influence of the different controlling circuits with 3-stage inverters and 1-stage inverter on the turn-on efficiency is gradually indistinct under the high current region. When the measured current is over ~ 2.5 A, no obvious difference of Vclamp between BFET1 and BFET2, both of which have the total channel widths of 2600 μm, is observed in Fig. 2.4(a). The phenomenon can be also attributed to the changes of the discharging paths. Under such high current region, the huge current can not be totally discharged by the channel of the main ESD clamp NMOS transistor. The parasitic npn bipolar transistor would be triggered on to discharge huge current. Therefore, the gate-driven enhancement by the 3-stage inverters will disappear under the high current region.

The similar measured results also can be observed in Modification1, Modification2, Modification3, and Modification4. Figs. 2.5(a) and 2.5(b) present the TLP I-V curves of the power-rail ESD clamp circuits with silicide blocking or without silicide blocking diffusions in the main ESD clamp NMOS transistor under the drain-contact-to-poly-gate spacing of 0.75 μm. These four TLP I-V curves have the similar trends, especially in the high current range.

The trigger voltages of Modification3 and Modification4 are lower than those of Modification1 and Modification2. The second breakdown currents (It2) of the designs with silicide blocking (Modification2 and Modification4) are higher than those without silicide blocking (Modification1 and Modification3), as shown in the insert of Fig. 2.5(a). The influence of the drain-side silicide blocking on the Ron and Vclamp is not obvious, as illustrated in Figs. 2.5(a) and 2.5(b). According to the TLP measured results, the design

scheme of controlling circuit would affect the trigger voltage of the power-rail ESD clamp circuit. However, the on resistance and Vclamp would be dominated by the drain-side layout style in the main ESD clamp NMOS transistor.

The HBM ESD robustness of the eight different power-rail ESD clamp circuits are listed in Table 2.2. The power-rail ESD clamp circuit with design of BFET2 sustains the highest HBM ESD stress of 7 kV. However, the ESD robustness of Tradition2 is below 6 kV. The four designs with the drain-contact-to-poly-gate spacing of 0.75 μm have the similar ESD robustness from 5.5 kV to 6.0 kV. The ESD robustness of these four designs do not have significant enhancement by depositing silicide blocking oxide layer on their drain-side diffusions of the main ESD clamp NMOS transistors or by adopting 3-stage inverters in the controlling circuit.

Table 2.2

HBM ESD Robustness of the Eight Power-Rail ESD Clamp Circuits

A faint relation between the ESD robustness and the controlling circuits (or the layout style of the main ESD clamp NMOS transistor) is summarized in Table 2.2. The 3-stage inverters in controlling circuit could be suitable for the main ESD clamp NMOS transistor

without silicide blocking on its diffusion. Such an NMOS transistor has a lower parasitic resistance on its surface channel. However, the controlling circuit with 3-stage inverters would induce some degradation on ESD robustness of the designs with drain-side silicide blocking in the main ESD clamp NMOS transistor. Therefore, based on the measured results of the TLP I-V characteristics and HBM ESD robustness, the 3-stage inverters in controlling circuit did not have improvement for the power-rail ESD clamp circuits in nanoscale CMOS technology.

2.2.4. Power-On Condition and Normal Circuit Operation Condition

In general, the normal VDD power-on voltage waveform of CMOS ICs has a rise time in the order of milli-second (ms). Due to such a slow rise time in normal power-on conditions, the ESD-transient detection circuit with a RC time constant of ~μs can distinguish the power-on signal to keep the main ESD clamp NMOS transistor off. All of the power-rail ESD clamp circuits studied in this work can successfully achieve this desired task under normal power-on conditions. However, the power-rail ESD clamp circuits with RC-based ESD transient detection circuits were easily mis-triggered to cause themselves into a “latch-on”

state, which the potential on VDD node will be continuously clamped at a lower voltage, under some abnormal fast power-on conditions [10], [11] or transient noise on VDD power lines [20], [21]. In this work, the eight different power-rail ESD clamp circuits were verified by a 1.2-V voltage pulse with 100-ns rise time, which is used to simulate the abnormal fast power-on condition, to investigate their immunities from the mis-trigger and latch-on state.

The measured results are respectively shown in Figs. 2.6 and 2.7. Unfortunately, the power-rail ESD clamp circuits with 3-stage inverters in controlling circuit present the worse immunity for mis-trigger under the 1.2-V fast power-on test conditions. BFET2 will be mis-triggered on to enter latch-on state under the 1.2-V fast power-on test condition. The voltage waveform is clamped at a very low voltage level around 0.3 V to 0.6 V, as illustrated in Fig. 2.6. Such phenomenon is much harmful for the applications of the power-rail ESD clamp circuits in real IC products. Besides, Modification3 also presents a similar measured result to that of BFET2. Tradition2 and Modification4, both of which have the silicide blocking on their drain sides, will be mis-triggered at the first 250 ns and first 420 ns, respectively, under the 1.2-V fast power-on test condition with 100-ns rise time. However, all of designs with 1-stage inverter in the controlling circuit, such as Tradition1, BFET1, Modification1, and Modification2, exhibit the higher mis-trigger immunity under this 1.2-V

fast power-on test condition. Their voltage waveforms can follow up with the fast power-on voltage waveforms, as presented in Figs. 2.6 and 2.7.

Fig. 2.6. The measured voltage waveforms of Tradition1, Tradition2, BFET1, and BFET2 under the 1.2-V fast power-on condition with 100-ns rise time.

Fig. 2.7. The measured voltage waveforms of Modification1, Modification2, Modification3, and Modification4 under the 1.2-V fast power-on condition with 100-ns rise time.

Although the 3-stage inverters for controlling circuit would enhance the gate-driven ability to slightly increase the ESD robustness and decrease Vclamp (and Ron), they will dramatically degrade the immunity against mis-trigger and latch-on issues under the fast power-on condition. Based on the aforementioned results, the controlling circuits with 1-stage inverter should be the optimal choice among the power-rail ESD clamp circuits with RC-based ESD-transient detection circuit.

2.3. Experimental Results in System-Level Test

2.3.1. Electrical Fast Transient (EFT) Test

The reliability of microelectronic products has been put more emphasis on the electromagnetic compatibility (EMC). In order to avoid the occurrence of the malfunction and mis-trigger during normal system operation conditions, the on-chip ESD protection circuits also has been required to meet the EMC regulation. For power-rail ESD clamp circuits, the impact of the transient noise coupled from microelectronic system on the power (or ground) line has attracted more attentions. The transient noise could induce some power-rail ESD clamp circuits into serious latch-on failure according to the previous studies [20], [21]. In this work, the electrical fast transient (EFT) test [52] has been applied on the eight different power-rail ESD clamp circuits to judge their immunities against fast transient noise on their power lines. The EFT voltage waveforms consist of many bursts with 15-ms duration and these bursts are repeated every 300 ms, as shown in Fig. 2.8(a). Besides, each voltage pulse in the burst has a rise time of 5 ns and a pulse width of 50 ns, as illustrated in Fig. 2.8(b). Moreover, because the minimum EFT voltage waveforms of 200 V provided by EFT generator would easily destroy the on-chip devices in nanoscale CMOS technology, the EFT voltage waveforms were decayed by a 100-time attenuator before they were directly applied to the VDD terminals of the power-rail ESD clamp circuits. The measurement setup for the EFT test was demonstrated in Fig. 2.9. Fig. 2.10(a) shows the measured results of BFET1 and BFET2 under the 4-V EFT test on the VDD terminals, both of which have the BFET (D= 0.25 μm without SB) layout styles for the main ESD clamp NMOS transistors.

The overshooting voltages on the VDD nodes can be effectively clamped by these two power-rail ESD clamp circuits. BFET1 exhibits a smooth waveform, only decaying the voltage amplitude on the VDD terminal, whereas BFET2 presents a rough waveform during the period of the EFT execution. Besides, the measured results of Tradition1 and Tradition2

have been illustrated in Fig. 2.10(b). The overshooting voltage on the VDD nodes also can be clamped by the designs with the traditional ESD clamp NMOS transistor (D= 2.0 μm with SB). Nevertheless, Tradition1 shows a smoother waveform during the period of the EFT execution. Based on the measured results in Figs. 2.10(a) and 2.10(b), the power-rail ESD clamp circuits with 1-stage inverter in controlling circuit possess better capability for clamping transient noise on VDD terminals.

(a)

(b)

Fig. 2.8. Specified electrical fast transient (EFT) waveforms of (a) burst, and (b) single pulse, with a repetition frequency of 5 kHz.

Fig. 2.9. Measurement setup for electrical fast transient (EFT) test on the DUT with the VDD bias of 1.2 V.

(a)

(b)

Fig. 2.10. Under the 4-V EFT voltage pulse, the measured voltage waveforms of (a) BFET1 and BFET2, and (b) Tradition1 and Tradition2.

With the 9.5-V EFT voltage stress on the VDD terminals, the measured results are presented in Figs. 2.11(a) and 2.11(b). All of the designs can efficiently clamp the overshooting voltage pulses on the VDD nodes during the EFT stresses. However, after the duration of the EFT voltage pulse, the voltage potential on VDD terminal is not successfully recovered to the normal operation voltage of 1.2 V in BFET2, as shown in Fig. 2.11(b).

(a)

(b)

Fig. 2.11. Under the 9.5-V EFT voltage pulse, the measured voltage waveforms of (a) BFET1 and BFET2, and (b) Tradition1 and Tradition2.

Although the voltage potential on VDD node would be slowly elevated toward 1.2 V, the huge conducting current from VDD to VSS does not vanish under the VDD node recovery to 1.2 V. The main ESD clamp NMOS transistor is still kept at on state after 9.5-V EFT stress, which is the occurrence of latch-on event. In contrast, the voltage waveforms of other designs can be quickly recovered to 1.2 V after the duration of the EFT voltage pulse and no

conducting current from VDD to VSS is observed after 9.5-V EFT stress. Moreover, according to the measured results in Fig. 2.11(b), the recovery period of Tradition2 is larger than that of Tradition1. Tradition2 would induce an irregular overshooting voltage pulse at the end of the duration of the EFT voltage pulse. In a nutshell, the RC-based ESD-transient detection circuit with the controlling circuit of 3-stage inverters and the main ESD clamp NMOS transistor with BFET (D= 0.25 μm without SB) layout style are very dangerous to be used as the power-rail ESD clamp circuit due to the mis-trigger and latch-on concern.

2.3.2. Latch-On Mechanism

According to the measured results of the EFT test and fast power-on condition, BFET2

According to the measured results of the EFT test and fast power-on condition, BFET2