HBM ESD Robustness

The HBM ESD robustness of the 1.8-V and 3.3-V analog I/O pins are shown in Table 6.3 and Table 6.4, respectively. In 1.8-V analog I/O pins, the ESD levels of the AIO_1, AIO_2, AIO_3, and AIO_4 are 0.5 kV, smaller than 0.5 kV, 0.5 kV, and 3.0 kV, respectively, in PS-mode ESD stress. Then, the PS-mode ESD levels of the AIO_1, AIO_2, AIO_3, and AIO_4 in 3.3-V analog I/O pins are 1.5 kV, smaller than 0.5 kV, 1.5 kV, and 2.0 kV, respectively. The analog I/O pins with the pure-diode protection have the higher ESDlevel

among all ESD test modes. In 1.8-V I/O designs, the ESD levels of the analog I/O pins with the MOS devices are much weaker than that with the diode devices during a PS-mode ESD stress. Ontheother hand, the ND-mode ESD levels don’tachievethegeneral specification(2 kV) in AIO_2 of1.8-V analog I/O pins, and AIO_2 and AIO_4 of 3.3-V analog I/O pins. The ESD robustness of the 1.8-V and 3.3-V I/O analog pins with MOS protection circuits are dominated by PS-mode ESD levels, but the analog pins with pure-diode protection circuits are dominated by ND-mode ESD levels. The difference in ESD robustness among analog I/O pins was inspected by failure analysis after PS-mode and ND-mode ESD stresses.

Table 6.3

The HBM ESD Robustness of 1.8-V Analog I/O Pins

Table 6.4

The HBM ESD Robustness of 3.3-V Analog I/O Pins

6.2.2. Failure Analysis

The I-V curves of 3.3-V and 1.8-V analog I/O pins were measured to identify which device or junction was damaged after PS-mode and ND-mode ESD stresses. The results are

listed in Table 6.5 and 6.6, respectively. The analog pins with GGNMOS and GDPMOS shorted to ground after PS-mode ESD stress. The 1.8-V and 3.3-V GGNMOS devices of the AIO_1, AIO_2, and AIO_3 were damaged to cause the short circuit between the analog pin and VSS.

Table 6.5

The Failures on the 1.8-V and 3.3-V Analog I/O Pins after PS-Mode ESD Stress

Table 6.6

The Failures on the 1.8-V and 3.3-V Analog I/O Pins after ND-Mode ESD Stress

The failure spot of 1.8-V analog I/O pins is shown in Figs. 6.5(a) and 6.5(b) after PS-mode ESD stress. After 0.5-kV or 1-kV ESD stresses, the AIO_1, AIO_2, and AIO_3 show local damage in GGNMOS. The ESD damage is located under poly gate oxide to cause the short circuit between analog pin to VSS, as shown in Fig. 7. On the other hand, the failure spots of the 3.3-V analog I/O pins are shown in Figs. 6.6(a) and 6.6(b) after PS-mode ESD stresses. In Fig. 6.6(a), the huge ESD current discharged through the parasitic npn bipolar transistor of the GGNMOS of AIO_3 to violently destroy the silicon substrate after 2-kV PS-mode ESD stress. The GGNMOS of AIO_2 shows only slight damage after 0.5-kV

PS-mode ESD stress, as shown in Fig. 6.6(b).

(a)

(b)

Fig. 6.5. (a) The failure spot is located at the GGNMOS in 1.8-V analog I/O pins with the MOS ESD protection design of AIO_2 after 0.5-kV PS-mode ESD stress. (b) The zoomed-in view of the failure spot.

Due to the difference in the turned-on efficiency of power-rail ESD clamp circuit of the AIO_1, AIO_2, and AIO_3, the distributions of the ESD current are also different in AIO_1, AIO_2, and AIO_3 of the 3.3-V analog I/O pins. In AIO_1 and AIO_3, the ESD current majority discharged through the drain-diode of the P-cell and the turned-on power-rail ESD clamp circuit to grounded VSS under PS-mode ESD stress. The parasitic npn bipolar transistor of the small GGNMOS would be turned on by the increasing voltage drop between

analog pin and VSS, and be destroyed to cause serious damages under higher ESD stresses.

But, the small GGNMOS of AIO_2 was unexpectedly turned on to discharge the ESD current and cause slight damage under lower ESD level, because the ineffective power-rail ESD clamp circuit didn’t provide the low-impedance discharging path. In addition, due to the lower drain-breakdown voltage and thinner gate oxide in the 1.8-V analog pins, the GGNMOS would be damage to cause regional failure spot under about 0.5-kV to 1-kV PS-mode ESD stress, as presented in Figs. 6.5(a) and 6.5(b).

(a)

(b)

Fig. 6.6. (a) The failure spot is located at the GGNMOS in 3.3-V analog I/O pin with the MOS ESD protection design of AIO_3 after 2.0-kV PS-mode ESD stress. (b) The failure spot is located at the GGNMOS in 3.3-V analog I/O pin with the MOS ESD protection design of AIO_2 after 0.5-kV PS-mode ESD stress.

However,themeasuredresults of the analog pins with pure diodes to implement N-cell and P-cellareobviously different. The I-V curves show that the VDD shorting to ground after PS-mode ESD stress. The power-rail ESD clamp devices are damaged to cause the short circuit between VDD and VSS in the 1.8-V and 3.3-V analog I/O pins, as shownin Figs.

6.7(a), 6.7(b), 6.8(a), and 6.8(b). In these SEM photographs, the failure spots are located at the parasitic npn transistors of the STFODs. The clearly destroyed path is occurred between the collector to the emitter of the parasitic npn bipolar transistor in the STFOD, as shown in Figs. 6.7(b) and 6.8(b).

(a)

(b)

Fig. 6.7. (a) The failure spot is located at the ESD clamp FOD in 1.8-V analog I/O pins with the pure-diode ESD protection design of AIO_4 after 3.5-kV PS-mode ESD stress. (b) The zoomed-in view of the failure spot.

(a)

(b)

Fig. 6.8. (a) The failure spot is located at the ESD clamp FOD in 3.3-V analog I/O pins with the pure-diode ESD protection design of AIO_4 after 2.5-kV PS-mode ESD stress. (b) The zoomed-in view of the failure spot.

The power-rail ESD clamp device will dominate the ESD levels of these analog I/O pins with the pure-diode under PS-mode ESD stress. The failures on the analog I/O pins after PS-mode ESD stress are summarized in Table 6.5. On the other hand, the failures on the analog I/O pins after ND-mode ESD stress are listed in Table 6.6. After the ND-mode ESD stress, the GDPMOS is damaged in those analog pins of AIO_1, AIO_2, or AIO_3 in 1.8-V and 3.3-V applications, as illustrated in Figs. 6.9(a) and 6.9(b). The parasitic pnp bipolar transistor of the GDPMOS was also turned on by the increased voltage drop between VDD and analog pin to seriously destroy under higher ND-mode ESD stress in AIO_1 and AIO_3 of the 1.8-V and 3.3-V analog I/O pins. Both the AIO_2 with a lower ESD level should be

also attributed to the ineffective power-rail ESD clamp circuit. According to the turn-on verification on the power-rail ESD clamp circuit, the STFOD could not rapidly discharge the ESD current to result in the GDPMOS conducting the huge current through the drain breakdown condition under lower ESD stresses, as shown in Fig. 6.9(b). The ESD levels of the analog I/O pins with the MOS ESD protection design are dominated by the ESD robustness of the GGNMOS and GDPOMS under PS-mode and ND-mode ESD stresses, respectively.

(a)

(b)

Fig. 6.9. (a) The failure spot is located at the GDPMOS in 1.8-V analog I/O pin with the MOS ESD protection design of AIO_1 after 3.0-kV ND-mode ESD stress. (b) The failure spot is located at the GDPMOS in 1.8-V analog I/O pin with the MOS ESD protection design of AIO_2 after 1.5-kV ND-mode ESD stress.