Discussion

The PMOS-triggered SCR devices have also been implemented in advanced CMOS technologies, such as 0.18-μm CMOS technology and 90-nm CMOS technology. According to the measured results of PMOS-triggered SCR devices in 0.18-μm CMOS technology, the PMOS-triggered SCR devices have the lower trigger voltage (below 3.6 V) and higher second breakdown current (over 4 A) to efficiently protect the internal circuits in deep-submicron CMOS technologies. In addition, the lower holding voltage and smaller

layout area of the SCR devices always are the advantageous to others devices, such as GGNMOS and parasitic lateral NPN bipolar transistor. According to the TLP I-V characteristics of the PMOS-triggered SCR devices, the holding voltages of the PMOS-triggered SCR devices are about 3 V (2.8 V) in 0.25-μm (0.18-μm) CMOS technology.

The holding voltages of parasitic diodes in SCR structures are about 0.85 V in 0.25-μm and 0.18-μm CMOS technologies. Due to these excellent ESD protection characteristics, which are lower trigger voltage and lower holding voltage, and higher ESD robustness with smaller layout area, the proposed initial-on ESD protection design with PMOS-triggered SCR device is suitable to apply in nanoscale CMOS technology. To decrease the voltage across the ultra-thin gate oxide of the internal circuits is the main challenge of ESD protection designs.

The overstress voltages across the ultra-thin gate oxide will induce the oxide breakdown to cause internal circuit damages. During the ESD stresses, the huge ESD voltages must be firstly clamp to avoid the damages of internal circuits. However, when the ESD currents discharged through the arranged ESD protection circuits, such as pad-to-VDD ESD clamp devices, pad-to-VSS ESD clamp devices, power-rail ESD clamp devices, VDD metal lines, or VSS metal lines, the voltage across the gate oxide were still raised by the holding voltages and IR drops of the ESD clamp devices, and IR drops of the VDD or VSS metal lines. The raised voltages across the gate oxide could cause the damages on the gate oxide of the internal circuits.

For the whole-chip ESD protection design scheme with PMOS-triggered SCR devices, the ESD currents can be discharged by the initially turned-on PMOS-triggered SCR device or parasitic diode in the SCR structure from the pad to the VSS, and then from VSS to VDD through the parasitic diode of another PMOS-triggered SCR device or the other initially turned-on PMOS-triggered SCR device in the power-rail ESD clamp circuit under different ESD-stress conditions. The detail ESD-current discharging paths were illustrated in Figs.

4.12(a), 4.12(b), 4.12(c), and 4.12(d). The discharging paths of PD-mode and ND-mode are longer than that of PS-mode and NS-mode. Therefore, when the ESD stress applied on an input pin, the raised voltage across the gate oxide of the PMOS transistor under PD-mode and ND-mode ESD stresses are higher than that of the NMOS transistor under PS-mode and NS-mode ESD stresses. Under PD-mode or ND-mode ESD stress, raised voltage (Voxide) across the gate oxide of the PMOS transistor can be simply evaluated by the holding voltages (Vh) of a PMOS-triggered SCR device and a parasitic diode, the IR drops of the ESD current (IESD) discharging through the on resistances (Ron) of a PMOS-triggered SCR device and a

parasitic diode, and the IR drops of the ESD current (IESD) discharging through the resistance (RM) of VSS metal line. The related equation of the raised voltage is shown as following. The raised voltages across the gate oxide of the PMOS transistor under PD-mode and ND-mode ESD stresses are shown in equation (4.1). The equations (4.2) and (4.3) are shown the raised voltages across the gate oxide of the NMOS transistor under PS-mode and NS-mode ESD stresses, respectively.

Voxide = Vh, SCR + Vh, diode + IESD × (Ron, SCR + Ron, diode + RM) (4.1)

Voxide = Vh, SCR + IESD × Ron, SCR (4.2)

Voxide = Vh, diode + IESD × Ron, diode (4.3)

The holding voltages of the PMOS-triggered SCR devices are about 3 V in 0.25-μm CMOS technology. The holding voltages of parasitic diodes in SCR structures are about 0.85 V in 0.25-μm CMOS technologies. The on resistances (Ron) of a PMOS-triggered SCR device and a parasitic diode in the SCR structure with the 50-μm device sizes are respectively about 2.5 Ω and 1.25 Ω. Generally, the resistances of the VSS metal lines or VDD metal lines are about several tens mini- Ω in deep-submicron CMOS technology. Before the gate-oxide breakdown of 12 V in the given 0.25-μm CMOS technology, the IESD can achieve over 2 A (about HBM ESD robustness of 3 kV) under the PD-mode or ND-mode ESD stress in the whole PMOS-triggered SCR devices with the device sizes of 50 μm. On the other hand, the IESD of the NS-mode or PS-mode ESD stress was higher than that of the PD-mode or ND-mode, because the whole-chip ESD protection design scheme with PMOS-triggered SCR devices had the shorter ESD discharging paths in NS-mode or PS-mode ESD stress.

For more advanced CMOS technology applications with the ultra thin gate oxide, the holding voltage and the on resistance (Ron) of the PMOS-triggered SCR devices needs to be further decreased to reduce the raised voltage across the ultra thin gate oxide of the internal circuits. However, the holding voltages of the SCR devices are dependent on the anode-to-cathode spacing of the SCR structures. The anode-to-cathode spacing of the PMOS-triggered SCR devices can be adjusted by the layout modifications of the embedded PMOS transistor, n-triggered node, and p-triggered node, such as the PMOS-triggered SCR devices with different layout styles of structure-1 and structure-2. The holding voltages of the PMOS-triggered SCR devices can be adjusted by different layout styles with different

anode-to-cathode distances to reduce for more advanced CMOS technology applications. The holding voltages would be reduced below 2 V in the SCR devices with the shortest anode-to-cathode spacing. In addition, the on resistances (Ron) of the PMOS-triggered SCR devices can be significantly reduced by increasing the device widths. The on resistances (Ron) of the PMOS-triggered SCR devices are directly proportional to the device widths. The ESD robustness also can be obviously improved in the increments of the device widths. Therefore, the PMOS-triggered SCR devices with the shorter anode-to-cathode spacing and large device width can efficiently reduce the raised voltage across the ultra thin gate oxide of the internal circuits for ESD protection applications in nanoscale CMOS technology.

4.5. Summary

The “initial-on” ESD protection concept realized by the PMOS-triggered SCR device with RC-based ESD-transient detection circuit has been successfully designed and verified in a 0.25-μm salicided CMOS process. Compared to the LVTSCR, the lowest trigger voltage and the highest turn-on efficiency of SCR device can be achieved by the proposed PMOS-triggered technique for effective on-chip ESD protection. Such a PMOS-triggered SCR also presents a high enough holding voltage to overcome the latchup issue under the normal circuit operation condition. The ESD robustness of the PMOS-triggered SCR can be higher than 5.5 kV with a device width of as small as 50 μm. Therefore, such initial-on SCR devices can achieve the whole-chip ESD protection scheme for input, output, power-rail ESD clamp circuit, and the ESD clamp cells between the separated power domains.

Chapter 5

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

As discussed in Chapter 4, the performance of initial-on SCR design implemented by PMOS-triggered SCR device has been proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. In this chapter, further optimizations on the PMOS-triggered SCR devices are presented. The modified PMOS-triggered SCR device with merged layout style is proposed to enhance its ESD protection capability. In addition, NMOS transistor is also embedded into the SCR structures to implement NMOS-triggered SCR devices. The device characteristics of these two different MOS-triggered SCR devices are compared to optimize the on-chip ESD protection design in CMOS ICs.

5.1. SCR Devices with Embedded MOS Transistors

The PMOS-triggered SCR device with embedded PMOS transistor and RC-based ESD transient detection circuit is shown in Fig. 5.1(a) [45]. The source and drain terminals of embedded PMOS transistors are respectively connected to the n-triggered and p-triggered nodes to synchronously generate double trigger currents into n-well and p-well of the SCR structure. The gate terminal of embedded PMOS transistor is tied to a RC-based ESD transient detection circuit. Compared to the PMOS-triggered SCR device, the NMOS-triggered SCR device is implemented with an embedded NMOS transistor, as shown in Fig. 5.1(b). The source and drain terminals of the embedded NMOS transistor are respectively connected to the p-triggered and n-triggered nodes. The gate terminal of embedded NMOS transistor is tied to a RC-based ESD transient detection circuit with an inverter. Due to the difference in the rise times between the ESD pulse and the VDD power-on voltage, the RC time constant in the ESD transient detection circuit is traditionally designed about 0.1~1 micro-second to distinguish the ESD stress condition from the normal circuit operation condition [6], [7]. To achieve the desirable operation, the RC time constant

of ESD transient detection circuit is designed as 0.4 μs in this work.

(a)

(b)

Fig. 5.1. Cross-sectional views of (a) the PMOS-triggered SCR device with RC-based ESD transient detection circuit, and (b) the NMOS-triggered SCR device with RC-based ESD transient detection circuit and an inverter.

Three different channel lengths (L), which are 0.3 μm, 0.5 μm, and 0.75 μm, of the embedded MOS transistors in the MOS-triggered SCR devices are investigated in this work.

The layout top views of the MOS-triggered SCR device are illustrated in Figs. 5.2(a) and 5.2(b). With the three different channel lengths in the embedded MOS transistors, the anode-to-cathode spacings are therefore different in the MOS-triggered SCR devices. They are 6.8 μm, 7.0 μm, and 7.25 μm in the MOS-triggered SCR devices with channel lengths of 0.3 μm, 0.5 μm, and 0.75 μm in the embedded MOS transistors, respectively. The MOS-triggered SCR device with merged layout style is also proposed and implemented in this work. The p-triggered node (or the n-triggered node) was directly merged into the drain side of the embedded PMOS transistor (or the embedded NMOS transistor), and located across the junction between n-well and p-well. The layout top views of the MOS-triggered SCR devices with shorter anode-to-cathode spacing are illustrated in Figs. 5.3(a) and 5.3(b).

This shorter anode-to-cathode spacing is only 5.1 μm with the channel length of 0.3 μm in the embedded MOS transistor. The device widths of all MOS-triggered SCR devices in this work are kept the same of 50 μm, which have been fabricated in a 0.18-μm fully-silicide CMOS process.

(a) (b)

Fig. 5.2. Top views of (a) the PMOS-triggered, and (b) the NMOS-triggered, SCR devices with three different channel lengths of 0.3 μm, 0.5 μm, and 0.75 μm in the embedded MOS transistor (original layout style).

(a) (b)

Fig. 5.3. Top views of (a) the PMOS-triggered SCR device, and (b) NMOS-triggered SCR device, with merged layout style. Both anode-to-cathode spacings of PMOS-triggered and NMOS-triggered SCR devices are only 5.1 μm.

5.2. Experimental Results

5.2.1. Device Characteristics of the MOS-Triggered SCR Devices

During the normal circuit operation condition with VDD and VSS biases, the gate terminals of embedded PMOS and NMOS transistors were biased at VDD and VSS respectively to keep themselves off. The measured DC I-V curves of the MOS-triggered SCR devices with different channel lengths in the embedded MOS transistors (original layout style) are shown in Figs. 5.4(a) and 5.4(b). The DC trigger voltage (Vt1) and holding voltage (Vh) of PMOS-triggered SCR device with 0.3-μm channel length are 7.30 V and 2.82 V, respectively. On the other hand, the NMOS-triggered SCR devices with 0.3-μm, 0.5-μm, and 0.75-μm channel lengths have the Vh of 3.28 V, 3.63 V, and 3.75 V, respectively. Their corresponding Vt1 are 6.50 V, 7.17 V, and 7.19 V. The Vt1 and Vh are increased by increasing the channel length of the embedded MOS transistor. Besides, according to the measured results in Figs. 5.5(a) and 5.5(b), the Vt1 of the MOS-triggered SCR device with merged layout style is similar to that with original layout style. However, the merged layout

style can slightly reduce the Vh of MOS-triggered SCR devices due to the shorter anode-to-cathode spacing in the layout. All Vh of MOS-triggered SCR devices with different channel lengths and different layout styles are still greater than VDD of 1.8 V in this work.

The DC Vt1 and Vh of PMOS-triggered and NMOS-triggered SCR devices were listed in Table 5.1, respectively. The difference in Vt1 between the NMOS-triggered and PMOS-triggered SCR devices can be attributed to the different drain breakdown voltages of NMOS and PMOS transistors.

(a)

(b)

Fig. 5.4. The DC I-V curves of (a) the PMOS-triggered, and (b) the NMOS-triggered, SCR devices with three different channel lengths in the embedded MOS transistors (original layout style).

(a)

(b)

Fig. 5.5. The DC I-V curves of (a) the PMOS-triggered, and (b) the NMOS-triggered, SCR devices under two different layout styles.

5.2.2. Turn-on Verifications of the MOS-Triggered SCR Devices

In order to observe the turn-on efficiency of the MOS-triggered SCR devices with different channel lengths in the embedded PMOS and NMOS transistors, a 5-V ESD-like voltage pulse with fast rise time of 2 ns was applied on each VDD terminal (anode) of the MOS-triggered SCR device with its VSS terminal (cathode) grounded. The rise time of Human-Body-Model (HBM) ESD event is about 2 ns to 10 ns [1]. The voltage pulse with a rise time of 2 ns generated from a pulse generator is used to simulate the fast rising edge of

HBM ESD event. The sharp-rising edge of the ESD-like voltage pulse will be detected by the RC-based ESD transient detection circuit and then to trigger on the MOS-triggered SCR devices. When the MOS-triggered SCR device is turned on, the voltage waveform on VDD node will be clamped down as the measured results shown in Figs. 5.6(a) and 5.6(b). The PMOS-triggered SCR device (original layout style) with 0.3-μm channel length in the embedded PMOS transistor can efficiently clamp the overshooting ESD voltage pulse to a lower voltage level, as shown in Fig. 5.6(a). However, all of NMOS-triggered SCR devices (original layout style) with 0.3-μm, 0.5-μm, and 0.75-μm channel lengths present high turn-on efficiency to clamp the voltage potentials at a much lower level. Due to the larger driving current capability in the embedded NMOS transistor, the NMOS-triggered SCR devices exhibit excellent turn-on efficiency, as illustrated in Fig. 5.6(b).

Table 5.1

Device Characteristics of PMOS-Triggered and NMOS-Triggered SCR Devices with Three Different Channel Lengths in Embedded MOS Transistors and Two Different Layout Styles

(a)

(b)

Fig. 5.6. Under 5-V ESD-like voltage pulses with 2-ns rise time, the clamped voltage waveforms by (a) the PMOS-triggered SCR devices, and (b) the NMOS-triggered SCR devices, under three different channel lengths in the embedded MOS transistors (original layout style).

5.2.3. TLP I-V Characteristics and ESD Robustness

The TLP [50] I-V curves of the MOS-triggered SCR devices with different channel lengths and layout styles in the embedded PMOS or NMOS transistors were shown in Figs.

5.7(a), 5.7(b), 5.8(a), and 5.8(b), respectively.

(a)

(b)

Fig. 5.7. (a) The TLP-measured I-V curves of the PMOS-triggered SCR devices with different channel lengths and different layout styles in the embedded PMOS transistors. (b) The zoomed-in view of (a) around the low-current range.

The trigger voltages (Vt1) of the PMOS-triggered SCR devices are decreased from

~5.12 V to ~3.50 V in the embedded PMOS transistors with 0.75-μm to 0.3-μm channel lengths, whereas those of the NMOS-triggered SCR devices are also decreased from ~2.98 V to ~2.47 V by decreasing the channel lengths from 0.75 μm to 0.3 μm. The shorter channel lengths in the embedded MOS transistors can generate the higher trigger currents to reduce the Vt1 of MOS-triggered SCR devices. The holding voltages (Vh) are decreased from ~3.38 V to ~2.81 V by decreasing the channel lengths from 0.75 μm to 0.3 μm in the embedded PMOS transistors, and those are similarly decreased from ~2.68 V to ~2.36 V by decreasing

the channel lengths in the embedded NMOS transistors. The on resistances (Ron), which are extracted from TLP-measured I-V curves, of the PMOS-triggered (or NMOS-triggered) SCR devices with 0.3-μm, 0.5-μm, and 0.75-μm channel lengths in the embedded PMOS transistors (or NMOS transistors) are 2.71 Ω, 3.28 Ω, and 3.31 Ω (or 2.60 Ω, 2.81 Ω, and 2.78 Ω), respectively, as listed in Table 5.1. The second breakdown currents (It2s) are increased from ~3.05 A to ~3.92 A (from ~2.67 A to ~2.78 A) by increasing the channel lengths from 0.3 μm to 0.75 μm in the PMOS-triggered (NMOS-triggered) SCR devices.

(a)

(b)

Fig. 5.8. (a) The TLP-measured I-V curves of the NMOS-triggered SCR devices with different channel lengths and different layout styles in the embedded NMOS transistors. (b) The zoomed-in view of (a) around the low-current range.

In addition, the HBM (MM) ESD robustness of the PMOS-triggered SCR devices with 0.3-μm, 0.5-μm, and 0.75-μm channel lengths are 5.0 kV (200 V), 6.5 kV (250 V), and 6.5 kV (300 V). They are 4.0 kV (150 V), 4.5 kV (200 V), and 4.5 kV (200 V) in NMOS-triggered SCR devices, as listed in Table I. Although the NMOS-triggered SCR devices have lower Vh and Ron, all of the PMOS-triggered SCR devices have the higher ESD robustness and It2. The reasons will be attributed to the different failure mechanisms in PMOS-triggered and NMOS-triggered SCR devices. Moreover, the MOS-triggered SCR device with merged layout style has a lower Vh, a smaller Ron, and a higher It2 due to a shorter anode-to-cathode spacing and higher turn-on efficiency. The It2 of the PMOS-triggered (NMOS-triggered) SCR device with merged layout style achieves 4.17 A (4.22 A), which is over 1-A higher than that with original layout style, as compared in Figs.

5.7(a) and 5.8(a). The HBM (MM) ESD robustness of the PMOS-triggered and NMOS-triggered SCR devices with merged layout styles are 7.0 kV (350 V) and 7.0 kV (350 V), respectively, in Table 5.1.

5.3. Failure Analysis and Discussion

5.3.1. Failure Analysis

The failure spot investigated by SEM image is located at the embedded PMOS transistor in the PMOS-triggered SCR device with 0.3-μm channel length, as shown in Fig. 5.9(a).

However, the failure spots are located at the anode diffusions of the PMOS-triggered SCR devices with 0.5-μm and 0.75-μm channel lengths, as shown in Figs. 5.9(b) and 5.9(c). The shorter channel length of 0.3 μm in the embedded PMOS transistor causes the crowding ESD currents nearby the embedded PMOS transistor, and generates the huge local joule heats to destroy the embedded PMOS transistor. In addition, the shorter channel length in the embedded PMOS transistors has the lower channel resistance to conduct the huge ESD current through the surface channel of PMOS transistor to cause ESD damages. On the other hand, since the driving capability of the NMOS transistor is higher than that of the PMOS transistor, the failure spots on all NMOS-triggered SCR devices are located in the embedded NMOS transistors after 4.5-kV or 5-kV HBM ESD stresses, as shown in Fig. 5.9(d). The embedded NMOS transistors conduct huge ESD currents, and the local joule heats are produced to damage the embedded NMOS transistor from drain to source. This failure mechanism can explain that the ESD robustness of NMOS-triggered SCR devices was not

increased by increasing the channel lengths of embedded NMOS transistors.

(a)

(b)

(c)

(d)

Fig. 5.9. (a) The failure spot is located at the embedded PMOS transistor in the PMOS-triggered SCR device with 0.3-μm channel length. (b) and (c) The failure spots are located at the anode to embedded PMOS transistors in the PMOS-triggered SCR devices with 0.5-μm and 0.75-μm channel lengths. (d) The failure spot is located at the embedded NMOS transistor in the NMOS-triggered SCR device with 0.75-μm channel length.

5.3.2. Discussion

According to the previous work [64], the holding voltage (Vh) of SCR device under DC measurement was much lower than that of the same SCR device under TLP measurement.

However, a different measured result has been observed in the NMOS-triggered SCR devices

However, a different measured result has been observed in the NMOS-triggered SCR devices