ESD Protection Circuit

Four ESD protection designs for analog I/O pins with 1.8-V and 3.3-V devices in a 0.18-µm CMOS process are compared in this work, as listed in Table I. The GGNMOS and GDPMOS with a channel width of 50 µm are used for pad-to-VSS (N-cell) and pad-to-VDD (P-cell) ESD protection, respectively. The silicide-blocking widths on drain side are 1.5 μm (1.91 μm) in all 1.8-V (3.3-V) MOS protection devices. The source sides of all 1.8-V (3.3-V) MOS protection devices were formed with silicidation. The HBM ESD robustness of the standalone GGNMOS or GDPMOS with such small dimension (50 μm) is less than 500V in the given 0.18-µm CMOS process when the GGNMOS or GDPMOS is zapped in the PS-mode or ND-mode ESD stresses (the devices in the drain-breakdown condition). However,

the 50-µm wide GGNMOS or GDPMOS can sustain an HBM ESD level of 6000 V in the same 0.18-µm CMOS process when the GGNMOS or GDPMOS is zapped in the negative-to-VSS (NS-mode) or positive-to-VDD (PD-mode) ESD stresses (the devices operated in the drain diode forward-biased condition). To avoid GGNMOS and GDPMOS into the drain breakdown condition, an efficient power-rail ESD clamp circuit is constructed in the analog I/O ESD protection circuits. In Fig. 6.1, the RC-based ESD-transient detection circuit [6], [7] is applied to trigger on the ESD clamp device to provide a low impedance path between the VDD and VSS, while the pad is zapped in the PS-mode or ND-mode ESD stresses. Because the power-rail ESD clamp device can be turned on under PS-mode or ND-mode ESD stresses, the ESD current is discharged through the forward-biased drain diode and the turned-on power-rail ESD clamp device, as illustrated in Fig. 6.1. The power-rail ESD clamp device is usually designed with a large device dimension to provide the higher ESD robustness and lower impedance path between VDD and VSS to effectively discharge ESD current under PS-mode or ND-mode ESD stresses. Because the ESD clamp device is added between VDD and VSS, the large parasitic junction capacitance of the ESD clamp device does not contribute to the analog pin. Therefore, this ESD protection design for analog pin can sustain a high ESD robustness but only with a low parasitic input capacitance.

Fig. 6.1. The power-rail ESD clamp circuit can provide a low-impedance path between VDD and VSS to discharge the ESD current under the PS-mode and ND-mode ESD stresses. ESD current is discharged through the P-cell (N-cell) and power-rail ESD clamp device during PS-mode (ND-mode) ESD stress.

In high-frequency analog circuit applications, the parasitic effects of ESD protection devices often play a critical factor to influence the circuit performance. Due to the smaller parasitic effect in the pure diode structure, the ESD protection design with pure diodes for input stage is more suitable than the ESD protection design with MOS devices in high-frequency circuit applications [65], [66]. In Table 6.1, the pure-diode ESD protection design between pad and VDD (VSS) is also designed to compare with the MOS protection circuit. The pure N+ diode and the pure P+ diode are constructed by the N+/P-well junction diode and the P+/N-well junction diode, respectively. The pure-diode ESD protection designs are drawn with the same equivalent perimeters as the channel width of the MOS devices in the test chip. In Table 6.1, the “P/D” terms mean the perimeters of the diode structures and the distances between N+ (P+) diffusions and the P+ (N+) diffusions in N+ diodes (P+

diodes), respectively, in pure-diode structures.

Table 6.1

Different ESD Protection Designs for 1.8-V and 3.3-V Analog I/O Pins

The turn-on efficiency of the ESD clamp devices with gate-driven and substrate-triggered designs had been studied in a 0.35-μm CMOS technology [67]. In this work, the gate-driven NMOS [7], substrate-triggered field oxide device (STFOD) [68], and

the substrate-triggered NMOS (STNMOS) with dummy gate [69] are used as the power-rail ESD clamp devices to verify the utility for the analog I/O pins in 0.18-μm CMOS technology, as shown in Table 6.1. The “W/L” terms in STFOD mean the perimeters (W) of the parasitic npn bipolar transistors in STFOD, and the distances (L) between the collector and the emitter of the parasitic npn bipolar transistors in STFOD. The STNMOS with dummy gate is a new proposed power-rail ESD clamp device, which has been drawn in the test chip and compared with gate-driven NMOS and STFOD. The device structures of gate-driven NMOS, STFOD, and STNMOS with dummy gate are shown in Figs. 6.2(a), 6.2(b), and 6.2(c), respectively.

VSS

Fig. 6.2. The cross-section views of (a) gate-driven NMOS, (b) substrate-triggered FOD (STFOD), and (c) substrate-triggered NMOS (STNMOS) with dummy gate.

In Fig. 6.2(c), the dummy gate is used to reduce the distance between the triggered note and the base of parasitic npn bipolar transistor in NMOS structure. It can improve the turn-on efficiency of STNMOS by enhancing the triggered current to achieve the base region of the npn bipolar transistor, as illustrated in Fig. 6.2(c). The silicide-blocking widths on collector side are 1.5 μm (1.5 μm) in 1.8-V (3.3-V) STFOD and STNMOS. Each analog I/O cell has been drawn in the same silicon area of an I/O cell with power-rail ESD clamp device and ESD-transient detection circuit. Therefore, all analog I/O cells have the same cell height of 89 μm (excluding the bonding pad) and cell pitch of 65 μm. In addition, each analog I/O pin was connected to the input stage of an inverter in the silicon chip to evaluate the core-circuit protection efficiency in each ESD test condition. Due to the transient gate oxide breakdown voltages as a function of the physical gate oxide thickness, the Transmission Line Pulse (TLP) measurement results of transient gate oxide breakdown voltages are 10-12 volts and 16-18 volts in 1.8-V and 3.3-V processes, respectively.