Fast Power-On Condition and Discussion

In general, the normal VDD power-on voltage waveform has a rise time in the order of milli-second (ms) and amplitude of VDD operation voltage. Due to such a slow rise time and small amplitude in normal power-on conditions, the coupling potential on the node A is too weak to turn on the switch NMOS transistor. Therefore, the main ESD clamp NMOS transistor will be well kept at off state. In this work, both power-rail ESD clamp circuits with the traditional and the new proposed ESD-transient detection circuits can successfully achieve this desirable task under normal power-on conditions. However, some previous studies [9]-[11], [20], [21] have illustrated that several power-rail ESD clamp circuits with RC-based ESD-transient detection circuits and feedback circuit schemes were easily mis-triggered and into the latch-on state under the fast power-on conditions with the rise time in the order of nano-second (ns). The design with the new proposed ESD-transient detection circuit has been applied with 1.2-V voltage pulses with 100-ns or 2-ns rise time, both of which are used to simulate the fast power-on condition, to investigate its immunities against the mis-trigger and latch-on event. The measured results are respectively shown in Figs. 3.8(a) and 3.8(b). Its measured voltage waveforms do not show any obvious degradation under the fast power-on condition with voltage pulse of 1.2 V and rise time of 100 ns or 2 ns. On the contrary, the power-rail ESD clamp circuit with the traditional ESD-transient detection circuit suffered from the mis-trigger under the fast power-on conditions. Its voltage waveforms will be slightly degraded under the 1.2-V fast power-on pulse with 100-ns rise time, and be dramatically degraded under that with 2-ns rise time. Since the feedback circuit schemes were not used in this work, the latch-on event was not observed in these two power-rail ESD clamp circuits. Compared with the results in the previous studies [9]-[11], [18], [19], the power-rail ESD clamp circuit with new proposed ESD-transient detection circuit possesses an excellent immunity against mis-trigger and latch-on event. Because the new proposed ESD-transient detection circuit adopts the capacitance coupling mechanism, this new proposed design not only distinguishes the abnormal overshooting voltage pulse by its rise time, but also discriminates this voltage pulse by its voltage amplitude. The new proposed ESD-transient detection circuit can easily distinguish the ESD event from the fast power-on condition with the voltage amplitude of 1.2 V and the rise time of 2 ns.

In addition, the electrical fast transient (EFT) test [52] is applied on the power-rail ESD clamp circuit with new proposed ESD-transient detection circuit to judge its immunity against fast transient noise on the power line. With 10-V EFT voltage stress on the VDD node,

the measured result is shown in Fig. 3.9. The new proposed design can efficiently clamp the overshooting voltage pulse on VDD node during EFT stress. After the duration of 10-V EFT voltage pulse, the voltage potential on VDD node is well remained at 1.2 V and no conducting current from VDD to VSS is observed. According to the EFT measured result, the new proposed ESD-transient detection circuit also possesses an excellent immunity against mis-trigger and latch-on event under electrical fast transient noise applied on VDD terminal.

(a) (b)

Fig. 3.8. The measured voltage waveforms of the power-rail ESD clamp circuits with the traditional and the new proposed ESD-transient detection circuits under the 1.2-V fast power-on conditions with (a) 100-ns rise time and (b) 2-ns rise time.

Fig. 3.9. Under the 10-V EFT voltage pulse, the measured voltage waveform of the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit.

3.4. Summary

A new proposed ESD-transient detection circuit cooperated with NMOS-based power-rail ESD clamp circuit has been presented and successfully verified in a 130-nm CMOS technology. The new proposed ESD-transient detection circuit adopts the capacitance coupling mechanism and a switch NMOS transistor to command the main ESD clamp NMOS transistor by the general controlling circuit with single-stage inverter. According to the measured results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit exhibits the superior ESD robustness of 8.0 kV and 400 V in HBM and MM ESD stresses, respectively. Moreover, it also possesses an excellent immunity against the mis-trigger and latch-on event under the 1.2-V fast power-on condition with the rise time of 2 ns.

Chapter 4

Implementation of Initial-On ESD Protection Concept with PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

In this chapter, a novel initial-on SCR design is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on SCR design is realized by circuit skill with the PMOS transistor in general CMOS processes [45]. This initial-on SCR design also presents a high enough holding voltage in a fully-silicided 0.25-μm CMOS process to avoid latchup issues in normal circuit operation conditions.

4.1. Background

In the past, the traditional ESD protection devices are initially kept off in CMOS ICs, as illustrated in Fig. 4.1. When the pad is zapped with ESD pulse, the ESD clamp device is triggered on by the ESD stress voltage to conduct ESD current from the pad to ground.

However, when the core circuits are realized with a much thinner gate oxide in a deep-submicron CMOS technology, the traditional ESD protection design cannot be able to effectively protect the core circuits with thinner gate oxide. To effectively protect the core circuits with much thinner gate oxide in the deep-submicron CMOS technology, a new on-chip ESD protection concept with the initial-on ESD protection device is shown in Fig.

4.2. The ESD clamp device is kept off, when the IC is in the normal circuit operation conditions. But, the ESD clamp device is initially on, when the IC is floating without any power bias. When the pad is zapped by ESD, the ESD clamp device standing in the already-on status can quickly discharge ESD current from the pad to ground. Therefore, this new ESD protection concept can effectively protect the internal circuits in a deep-submicron CMOS technology [62]. The optimum ESD protection design window is restricted within the

range between VDD operation voltage and the gate oxide breakdown voltage. The ESD protection circuits should be triggered on to discharge the ESD currents, and to protect the internal circuits without gate oxide damage. Therefore, the trigger voltage of the ESD protection circuit must be lower than the breakdown voltage of the internal circuits. In addition, the holding voltage and on resistance (Ron) of ESD protection circuit will significantly influence the ESD robustness of CMOS IC product. The lower holding voltage and smaller on resistance (Ron) can provide more efficient ESD protection. However, the holding voltage of ESD protection devices must be higher than the VDD operation voltage to prevent the latchup under normal circuit operation condition [63]. In IC products, the on-chip ESD protection designs are required to provide higher ESD robustness with smaller layout area to save the chip area. Silicon controlled rectifiers (SCRs) have been used as on-chip ESD protection devices, because of their superior area-efficient ESD robustness [22]. However, SCR has some drawbacks, such as higher trigger voltage (Vt1), lower turn-on efficiency, and even latchup danger.

Fig. 4.1. The traditional ESD protection design with the initial-off ESD protection device. (a) The ESD clamp device was kept off in normal circuit operation conditions. (b) During ESD stress, the ESD clamp device was triggered on to discharge ESD current.

The related previous studies [22]-[31] on solving the disadvantages have been reported in Chapter 1. In this chapter, a novel initial-on SCR design implemented by PMOS-triggered SCR device is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on SCR design is realized by circuit skill with the embedded PMOS transistor cooperated with RC-based ESD-transient detection circuit in general CMOS processes [45]. This initial-on SCR design has a high enough

holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-μm CMOS process.

PAD

Fig. 4.2. The new ESD protection concept with the initial-on ESD protection device. (a) The ESD clamp device was kept off in normal circuit operation conditions. (b) The ESD clamp device was initially on when IC was floating. (c) The already-on ESD clamp device can rapidly discharge ESD current during ESD stress.

4.2. Realization of the Initial-On SCR Design

4.2.1. Implementation of the Initial-On ESD Protection Circuit

The new proposed initial-on ESD protection design, which consists of the SCR device with PMOS-triggered technique and the RC-based ESD transient detection circuit, is shown in Fig. 4.3. A PMOS transistor is directly embedded into the SCR structure to achieve the initial-on function for ESD protection. The source and drain terminals of the PMOS transistor are connected to the additional n+ diffusion and p+ diffusion of the SCR structure, respectively, as illustrated in Fig. 4.3. These additional p+ diffusion and n+ diffusion are the

p-triggered and n-triggered nodes in p-substrate and n-well of this SCR structure, respectively, to enhance the turn-on efficiency of SCR during ESD stress. The gate terminal of the embedded PMOS is controlled by a RC-based ESD transient detection circuit, which is used to distinguish the ESD-stress conditions from the normal circuit operation conditions.

P+ N+ P+ P+ P+ N+ P+ N+

Fig. 4.3. The cross-sectional view of the initial-on SCR design with PMOS-triggered technique.

4.2.2. Operation Principles

Under positive VDD-to-VSS ESD-stress condition, the gate voltage of embedded PMOS is initially kept at zero in the power-rail ESD clamp circuit, as shown in Fig. 4.4(a). With an initial gate voltage of 0 V, the PMOS transistor is initially on to conduct the ESD current from the anode (P+) of SCR or pickup (N+) of n-well, and then inject into the p-well/p-substrate of SCR device, as the dashed lines illustrated in Fig. 4.4(a). With the both trigger currents in the n-well and p-well/p-substrate synchronously, the SCR can be fired on quickly. Finally, the ESD current is mainly discharged from the anode to the cathode of SCR device. The equivalent circuit of the initial-on SCR design is shown in Fig. 4.4(b). The initial-on PMOS transistor provides the conduction paths to generate the voltage bias between emitters and bases, which in turns induce base currents of the parasitic vertical pnp bipolar transistor (Qpnp) and lateral npn bipolar transistor (Qnpn) to trigger on the SCR device to discharge ESD current. Due to the difference in the rise time between the ESD pulse and the VDD power-on voltage, the RC time constant of the ESD-transient detection circuit is designed about 0.1~1 micro-second to distinguish the ESD-stress condition from the normal

circuit operation condition [6], [7]. To achieve the desired operation, the RC time constant of the ESD-transient detection circuit in Figs. 4.4(a) and 4.4(b) is designed around 1 μs in this work. During normal circuit operation condition with the normal VDD and VSS power supplies, the gate of embedded PMOS is biased at VDD to keep itself off. Therefore, the PMOS-triggered SCR device is always kept off during the normal circuit operation condition.

VDD

Fig. 4.4. (a) The operation of the initial-on SCR design for power-rail ESD clamp circuit. (b) The equivalent circuit of the initial-on SCR design. The embedded PMOS transistor generates the trigger current to initiate the turn-on of SCR during ESD stress.

4.2.3. Layout Structure for Initial-On SCR Device

To investigate the turn-on phenomena and circuit characteristics, two types of layout implementations (structure-1 and structure-2) for the proposed initial-on SCR device are verified in this work, as shown in Figs. 4.5(a) and 4.5(b). The SCR structure is consisted of P+

diffusion of anode, the n-well, the p-substrate (p-well), and the N+ diffusion of cathode in each test structure. The embedded PMOS transistors of structure-1 and structure-2 are different in the layout of the n-triggered node and the anode-to-cathode spacing. Because the n-triggered node has been merged into the source terminal of PMOS transistor, the anode-to-cathode spacing of structure-2 is reduced to 7.7 μm, whereas the anode-to-cathode spacing of structure-1 is 9.5 μm in a 0.25-μm CMOS process. The device characteristics, such as holding voltage, on resistance (Ron), and ESD robustness, of the PMOS-triggered SCR device can be adjusted by its anode-to-cathode spacing.

50 μm

Fig. 4.5. The top views of initial-on SCR devices with (a) structure-1 and (b) structure-2 layout styles realized in a 0.25-μm CMOS process.

4.3. Experimental Results

The initial-on SCR devices, in Figs. 4.5(a) and 4.5(b), have been fabricated in a 0.25-μm salicided CMOS process without using the silicide-blocking mask. The active width of each SCRdeviceis drawn with 50 μm in the test chip.

4.3.1. DC Characteristics for the Initial-On SCR Devices

According to the measured device DC characteristics, the breakdown voltages of the P+

drain diffusion/n-well junction in PMOS and N+ drain diffusion/p-well junction in NMOS are respectively 7 V and 6.5 V in the 0.25-μm CMOS process. The n-well/p-well junction breakdown voltage is higher than 15 V in the same CMOS process. If the ESD protection devices are triggered on by junction-breakdown mechanisms, such as gate-grounded NMOS (GGNMOS), gate-VDD PMOS (GDPMOS), and LVTSCR, the junction-breakdown mechanisms often have higher trigger voltages which could not efficiently protect the internal circuits with thinner gate oxide in the deep-submicron or nanoscale CMOS technologies.

Therefore, the initial-on ESD protection concept realized with PMOS-triggered SCR device is proposed in this work to achieve the lower trigger voltage and the higher turn-on efficiency.

In order to observe the influence of embedded PMOS gate bias on the trigger voltage of SCR

devices, the gate-biased voltages (VG) of 0, 1, 2, and 3 V were applied to the gate terminal of the embedded PMOS transistor. The measurement setup is shown in Fig. 4.6(a). The measured DC I-V curves of the initial-on SCR devices with structure-1 and structure-2 layout styles under different gate-biased voltages are shown in Figs. 4.6(b)and 4.6(c),respectively.

P+

Fig. 4.6. (a) The different gate-biased voltages were applied to the gate terminal of the embedded PMOS transistor in the SCR structure. The measured DC I-V curves of the initial-on SCR devices with the layout styles of (b) structure-1, and (c) structure-2, under different gate-biased voltages.

The trigger voltage (Vt1)of PMOS-triggeredSCR device is reduced with the decrease of the gate-biased voltage. When the gate voltage of the embedded PMOS is decreased from 3 V to 0 V, the Vt1 of PMOS-triggered SCR device is decreased from ~6.6 V to ~4 V and from

~5.75 V to ~3.3 V in structure-1 and stricture-2, respectively. These results have proven that the Vt1 of SCR device can be significantly reduced by the proposed PMOS-triggered technique. The holding voltage of the PMOS-triggered SCR device is slightly increased when the gate voltage of embedded PMOS is increased, as shown in Figs. 4.6(b) and 4.6(c). With an initial gate voltage of 0 V, the SCR device has the lowest holding voltage to effectively clamp the over-stress ESD pulse. In addition, another issue of using SCR device as the ESD protection device is the latchup concern under normal circuit operation condition. The gate terminal of the embedded PMOS transistor was biased at VDD through the resistor in the ESD-transient detection circuit during normal circuit operation conditions. To avoid latchup issue, the holding voltage of SCR devices must be designed greater than the maximum voltage of VDD. Under the temperatures of 25, 75, and 125 ^oC, the holding voltages of PMOS-triggered SCR devices in the layout styles of structure-1 and structure-2 with gate bias at VDD were shown in Figs. 4.7(a) and 4.7(b), respectively. The dependence of SCR holding voltages in structure-1 and structure-2 layout styles on the operating temperature is shown in Fig. 4.7(c). The holding voltages of the PMOS-triggered SCR device in structure-1 layout style are about ~3.15 V to ~2.65, which is higher than the 2.5-V VDD voltage, under operating temperatures of 25 to 125 ^oC. The holding voltages of the PMOS-triggered SCR device in structure-2 layout style are about ~2.78 V to ~2.45 under operating temperatures of 25 to 125 ^oC. A diode can be added in series with the PMOS-triggered SCR device of structure-2 to further increase the total holding voltage for latchup-free applications in the CMOS ICs with VDD of 2.5 V.

Temperature (oC)

Fig. 4.7. The DC I-V curves of the initial-on SCR devices with the layout styles of (a) structure-1, and (b) structure-2, under different temperatures. (c) The dependence of SCR holding voltage on the temperature.

4.3.2. Turn-on Verification

To observe the turn-on efficiency of the initial-on SCR device, 6-V ESD-like voltage pulses with different rise times were applied on the anodes of PMOS-triggered SCR with structure-1, structure-2, and the traditional LVTSCR [23]. The measurement setup for investigating the turn-on efficiency of the initial-on SCR device is illustrated in Fig. 4.8(a).

The rise time of Human Body Model (HBM) ESD event is about 2 ns to 10 ns [1]. The

clamped voltage waveforms by different SCR devices are compared in Figs. 4.8(b) and 4.8(c) under the rise times of 10 ns and 1.8 ns, respectively.

P+

Time (1ns/div)

Fig. 4.8. (a) The measurement setup with ESD-like voltage pulse to investigate the turn-on efficiency of the LVTSCR and the PMOS-triggered SCR in structure-1 and structure-2 layout styles.

The 6-V ESD-like voltage pulses were applied to the anodes of SCR devices with the rise time of (b) 10 ns and (c) 1.8 ns. (d) The zoomed-in view on the clamped voltage waveform of (c) around the rising edge.

In Fig. 4.8(b), the applied 6-V ESD-like voltage pulse with a rise time of 10 ns is clamped by the PMOS-triggered SCR devices to a lower voltage level (below 4 V). In Fig.

4.8(c) with a rise time of as short as 1.8 ns which is faster than the typical rise time of HBM ESD event, the PMOS-triggered SCR devices performed a lower trigger voltage and higher turn-on efficiency than LVTSCR did. Because the LVTSCR device was triggered by junction breakdown occurring between p-well and the N+ drain diffusion of the embedded GGNMOS transistor, the trigger voltage of LVTSCR was much higher than that of the proposed PMOS-triggered SCR device. When the 6-V ESD-like voltage pulses with the rise time of 10 ns or 1.8 ns were applied on the PMOS-triggered SCR devices, the main SCR structures were rapidly turned on by the PMOS-generated trigger current. However, the LVTSCR device can not be turned on to clamp the overshooting ESD voltage pulses when the 6-V ESD-like voltage pulses were applied. According to the measurement results in Figs. 4.8(b) and 4.8(c), the PMOS-triggered SCR devices can be firstly turned on at a lower applied voltage pulse to efficiently clamp the overshooting ESD voltage pulse to a lower voltage level (below 4 V) at the short period. The rising edges of the voltage waveforms clearly prove the higher turn-on efficiency of the new proposed initial-on SCR devices under both structure-1 and structure-2