Proposed Solutions to Rescue such ESD Failures

To overcome such ESD failures at the interface circuits between separated power domains, adding the suitable blocking resistors (Rblock) to the interface devices and installing the bi-directional diode connection in original ESD protection scheme were proposed in Fig. 7.8. Two extra blocking resistors are added at the source terminal of the M1 and the gate terminal of the Mb, respectively. The bi-directional diode connection was used to connect the separated ground lines (VSS1 and VSS2). The diode numbers of the bi-directional diode connection were optimized to prevent different ground-line noise coupling issue between the separated ground lines of analog and digital circuit blocks. To further provide higher ground-line noise coupling isolation, the bi-directional silicon-controlled rectifier (SCR) [72] with ESD-detection circuit can be used to replace the bi-directional diode connection between the separated power lines (VDD1 and VDD2). By using the proposed ESD protection solutions, the ESD current will be effectively discharged along the desired connection of ground lines under ND-mode MM ESD stress. In addition, the blocking resistors also can avoid the ESD currents discharging through the undesirable paths. Therefore, the abnormal internal ESD damages can be overcome in this IC product with separated power lines.

Fig. 7.8. The proposed ESD protection solution to rescue ESD failures at the interface circuits of this IC product with separated power domains.

7.2. Active ESD Protection Designs for Interface Circuits between Separated Power Domains

7.2.1. ESD Threats and Damages of Interface Circuits between Separated Power Domains

With more circuit blocks integrated into an IC product to meet different applications, such circuit blocks usually have separated power domains to supply the power and ground signals in each individual circuit block. In addition, the interface circuits were also adopted to communicate with different circuit blocks inside the chip. However, the interface circuits between separated power domains are often damaged under cross-power-domain ESD stresses [33]-[38]. The bi-directional diode connections between the separated power domains are usually applied to construct a completely whole-chip ESD protection design [39], [40], as shown in Fig. 7.8. In general, the bi-directional diode connections are only used to connect the separated VSS pins due to different VDD1 and VDD2 voltage levels and noise-coupling considerations [39], [40]. When the ESD voltage was applied on the VDD1 and grounded VDD2 under the cross-power-domain ESD stresses, the ESD current can be discharged from the VDD1 to the VSS1 by the power-rail ESD clamp circuit 1 in the power domain one, from the VSS1 to the VSS2 through the inserted bi-directional diode connection, and then from the VSS2 to the grounded VDD2 through the other power-rail ESD clamp circuit 2 in the power domain two, as the discharged path shown by dashed line in Fig. 7.9(a). The Vh1 and Vh2 are the holding voltage of the power-rail ESD clamp circuits 1 and 2, respectively. Then, the Vhd is the holding voltage of the bi-directional diode connection between the separated power domains. Among the parameters, the R1, R2, and Rd are the turn-on resistances of the power-rail ESD clamp circuits 1, 2, and the bi-directional diode connection, respectively.

When the ESD current was conducted by this long discharging path, it would induce the overstress voltage across the each MOS transistor in interface circuits between separated power domains [40]-[42]. The induced voltage drops with discharging ESD currents from VDD1 to VDD2 on each node of the interface circuit had been estimated, as shown in Fig.

7.9(a). The voltage potential at node A could be raised up to the VDD1 because the driver’s PMOS transistor (Mp1) had an initially floating gate situation. The highest voltage drop was applied across the gate oxide of the receiver’s PMOS transistor (Mp2) in interface circuits under the VDD1 to VDD2 ESD stresses. On the other hand, the highest voltage drop was also generated across the gate oxide of the receiver’s NMOS transistor (Mn2) in interface circuits

under the VDD1 to VSS2 ESD stresses. The similar estimation on voltage drops during ESD stress was presented in Fig. 7.9(b).

(a)

(b)

Fig. 7.9. The estimations of the induced voltage potential under the cross-power-domain (a) VDD1-to-VDD2, and (b) VDD1-to-VSS2, ESD stresses.

Therefore, the 2^nd ESD clamp designs were usually installed nearby the MOS transistors of receiver to reduce the overstress voltage under the cross-power-domain ESD stresses

[40]-[42], as shown in Figs. 7.9(a) and 7.9(b). As the CMOS technologies being continually shrunk toward nanometer scales, the breakdown voltages of ultra-thin gate oxide in the MOS transistors were sharply reduced to impact the ESD protection designs. It was important to avoid the gate oxide damages of the MOS transistors in the interface circuits by ESD-current induced overstress voltages. The overview on some 2^nd ESD clamp designs will be presented and compared in the following sub-section.

7.2.2. Review on ESD Protection Designs for Interface Circuits between Separated Power Domains

The resistor-diode clamp design [40], which consists of a resistor (R1) and two diodes, was allocated in the interface circuits between separated power domains in order to restrict the ESD current distribution and to clamp the overstress voltage across the gate oxide of the receiver’s MOS transistors, as shown in Fig. 7.10.

Fig. 7.10. The ESD protection design with resistor-diode clamp had been proposed to protect the interface circuits between separated power domains [40].

These two clamped diodes can be respectively replaced by the gate-grounded NMOS (GGNMOS) transistor and gate-VDD PMOS (GDPMOS) transistor to further enhance the clamping efficiency. However, such traditional junction-breakdown clamp designs with diodes, GGNMOS, or GDPMOS could not be suitable for interface circuits with ultra-thin oxide against cross-power-domain ESD stresses. Therefore, some second ESD protection

designs with special trigger mechanisms, such as the modified interface circuits with special drivers and receivers [41] as well as the ground-current-trigger (GCT) NMOS transistor [42], had been proposed to efficiently reduce the overstress voltages across the ultra-thin gate oxides of the MOS transistors in interface circuits between separated power domains.

(a)

(b)

Fig. 7.11. The ESD protection design with (a) a special driver and (b) a special receiver for interface circuits between separated power domains [41].

The special driver and receiver had been implemented for interface circuits between separated power domains, which were collaborated with an ESD detector to accomplish

differently desired functions under the cross-power-domain ESD stress condition and the normal circuit operation condition, as presented in Figs. 7.11(a) and 7.11(b) [41]. The special driver was composed of a 1-stage NAND gate and a 1-stage inverter. Through different signals from the ESD detector, the driver can be respectively performed as cascaded 2-stage inverters and a biased-high 1-stage inverter under normal circuit operation condition and VDD1-to-VDD-2 cross-power-domain ESD stress, as illustrated in Fig. 7.11(a). In addition, the special receiver consisted of a 1-stage inverter, a PMOS transistor (Mp3) cascoded on the inverter, and a NMOS transistor (Mn3) in parallel to the inverter. The cascoded PMOS and the parallel NMOS transistors, both of which were controlled by the ESD detector, will be respectively turned on and off under normal circuit operation condition, whereas the Mp3 and the Mn3 will be respectively turned off and on under cross-power-domain ESD stress, as shown in Fig. 7.11(b). Although such special designs in the driver and receiver [41] can reduce and restrain the overstress voltage across the gate oxide of receiver’s PMOS and NMOS transistors, the complicated connection could be an obstacle to practical applications.

Fig. 7.12. The ESD protection design with grounded-current-trigger (GCT) NMOS transistor for interface circuits between separated power domains [42].

On the other hand, the grounded-current-trigger (GCT) NMOS transistor [42] had been also proposed to act as a 2^nd ESD clamp for interface circuits between separated power domains, as shown in Fig. 7.12. The GCT NMOS transistor can be turned on to clamp the overstress voltage across the gate oxide of receiver’s PMOS and NMOS transistors by the

induced voltage drop between VSS1 and VSS2 under cross-power-domain ESD stress. But, it will be kept off due to the same voltage potential on VSS1 and VSS2 under normal circuit operation condition. This active 2^nd ESD clamp design can achieve high ESD robustness under cross-power-domain ESD stress [42]. In this work, one new active ESD protection design for interface circuits between separated power domains was proposed to solve this problem.

7.3. New Cross-Power-Domain ESD Protection Design

7.3.1. Implementation of the New Proposed Design for Cross-Power-Domain ESD Protection

An ESD protection design was implemented by gate-controlled PMOS (GC-PMOS) and gate-controlled NMOS (GC-NMOS) transistors with the ESD-transition detection function for interface circuits between separated power domains, as shown in Fig. 7.13. The GC-PMOS (Mp3) and GC-NMOS (Mn3) were placed nearby the receiver in the interface circuits to clamp overstress voltages across the gate oxides of the receiver’s NMOS and PMOS transistors (Mn2 and Mp2), respectively. The gate terminals of GC-PMOS and GC-NMOS transistors were respectively connected to the VDD2 and VSS2 through the 1-kΩ resistance. The 1-kΩ resistances are adopted to avoid the gate-oxide damages to GC-PMOS and GC-NMOS transistors during the ESD stresses. During the VDD1-to-VSS2 cross-power-domain ESD stress, the positive ESD voltage was applied at the VDD1 with the grounded VSS2. The gate-to-source voltage (Vgs) of the GC-PMOS transistor (Mp3) was high enough to turn this Mp3 on under VDD2 floating. The voltage potential of node A can be clamped by the turn-on Mp3 to restrict the overstress voltage across the receiver’s NMOS transistor (Mn2). When the negative ESD voltage was applied at VDD1 with the grounded VSS2, the forward-biased parasitic diode, which was consisted of N-well and P+ drain diffusion in Mp3, will provide excellent ability to clamp the voltage across Mn2. In addition, the GC-NMOS transistor (Mn3) was useful to prevent ESD damage under the VDD1-to-VDD2 ESD stresses. When the positive ESD voltage was applied at the VDD1 with the grounded VDD2, the ESD current initially discharged by the desired path, which was the dashed line in Fig. 7.9(a). This ESD discharging current will induce the voltage levels on VDD1, VDD2, VSS1, and VSS2. The induced voltage level of VSS2 was higher than that of VDD2 under the positive VDD1-to-VDD2 ESD stresses. The GC-NMOS

transistor (Mn3) can be turned on by the induced voltage levels of VSS2 and VDD2. Then, the voltage level at node A can be restricted to avoid damages to the gate oxide in the interface circuits. The GC-NMOS transistor can also be turned on in the negative ESD stresses since the voltage level at node A would be lower than that of VSS2. On the other hand, the parasitic npn bipolar transistor in Mn3 can be triggered on to restrict the voltages across the gate oxides of Mn2 and Mp2 under VDD1-to-VDD2 ESD stresses.

Fig. 7.13. A proposed cross-power-domain ESD protection design with gate-controlled PMOS and NMOS (GC-PMOS and GC-NMOS) transistors and source pumping mechanism.

According to previous studies, gate oxide breakdown voltages of gate-to-source terminals and gate-to-bulk terminals are quite different in NMOS transistors [73]. The gate oxide breakdown voltage of gate-to-source terminal is remarkably lower than that of gate-to-bulk terminal. In order to enhance the ESD robustness of the input stage with thin gate oxide in nanoscale CMOS process and extend the design windows of ESD protection circuits, the source pumping design had been used to reduce the ESD voltage across the gate-to-source terminal in the NMOS transistor of input stage under HBM and CDM ESD stresses [73], [74].

In Fig. 7.13, a resistor had also been inserted between VDD2 (or VSS2) and source terminal of Mp2 (or Mn2) to comprise source pumping mechanism. The partial ESD currents could be conducted by turned-on Mp3 and Mn3, also raised the source-terminal potentials of Mn2 and

Mp2 to reduce the voltage across the gate-to-source terminals of Mn2 and Mp2. The source pumping mechanisms can be expected to further enhance the ESD robustness of the receivers in interface circuits under the cross-power-domain ESD stresses.

7.3.2. Experimental Results

The cross-power-domain ESD protection design with the GC-PMOS and GC-NMOS transistors had been implemented in 0.13-μm 1.2-V CMOS process. Two other different cross-power-domain ESD protection designs, which were diodes [40] and ground-current-triggered (GCT) NMOS transistor [42], were also compared with the design with GC-PMOS and GC-NMOS transistors under the same process. The cross-power-domain ESD protection design with diodes was identical with the aforementioned scheme, as shown in Fig. 7.10. However, the GCT NMOS transistor was only substituted for the GC-PMOS transistor to construct a complete cross-power-domain ESD protection in this work, as shown in Fig 7.14.

Fig. 7.14. The cross-power-domain ESD protection design with GCT NMOS and GC-NMOS transistors and source pumping mechanism.

Both device sizes (W/L) of the gate-controlled PMOS (Mp3) and NMOS (Mn3) transistors are 5 μm / 0.18 μm. Then, the value of R1 is 25 Ω. Because the ESD currents were not mainly discharged by the Mn3 and Mp3, these transistors did not need to occupy huge device dimensions. The equivalent perimeters of the diodes are 5 μm, and the device size (W/L) of the GCT NMOS transistor is also 5 μm / 0.18 μm in this work. These

cross-power-domain ESD protection designs had the identical ESD protection elements of the power-rail ESD clamp circuit in each power domain and the bi-directional diode connection between separated power domains. The I-V characteristics of these three designs were measured by transmission-line-pulse (TLP) system, which generated the current pulses with 100-ns duration time and 10-ns rise time to be able to obtain the device characteristics under high-current stresses [50].

The TLP I-V characteristics of the cross-power-domain ESD protection design with the GC-PMOS and GC-NMOS transistors under VDD1-to-VSS1, VSS1-to-VSS2, and VSS2-to-VDD2 three different stress combinations had been measured and illustrated in Fig.

7.15(a). The symbol of VDD1-to-VSS1 (VSS1-to-VSS2 or VSS2-to-VDD2) means that the TLP current pulse was applied at the VDD1 (VSS1 or VSS2) under the grounded VSS1 (VSS2 or VDD2). Therefore, the VDD1-to-VSS1 curve presents the TLP I-V characteristic of a power-rail ESD clamp circuit which consists of RC-based ESD-transient detection circuit and main power-rail ESD clamp NMOS transistor between VDD1 and VSS1. Then, the VSS1-to-VSS2 is the TLP I-V characteristic of the bi-directional diode connection between VSS1 and VSS2, while the VSS2-to-VDD2 is the TLP I-V characteristic of the parasitic drain-bulk diode in the power-rail ESD clamp NMOS transistor between VSS2 and VDD2.

Moreover, the TLP measured results of all three different cross-power-domain ESD protection designs were shown in Fig. 7.15(b). Under the VDD1-to-VSS2 stresses, these three different cross-power-domain ESD protection designs presented high second breakdown currents (It2). The cross-power-domain ESD protection design with GC-PMOS and GC-NMOS transistors had the highest It2 value about 3.52 A. The HBM and MM ESD robustness of these three designs were presented in Table 7.2, under VDD1-to-VSS2 and VDD1-to-VDD2 ESD stresses. The new proposed ESD design had the highest ESD robustness among all ESD stresses. However, the cross-power-domain ESD protection design with diodes presented an unexpected ESD robustness under VDD1-to-VDD2 ESD stresses.

The related attributions of the low ESD robustness in the design with diodes would be discussed and explained by failure analyzing in following section.

In addition, the influence of source pumping mechanism was investigated in cross-power-domain ESD protection designs with GCT NMOS transistor. The comparisons between the cross-power-domain ESD protection designs with and without source pumping resistance were shown in Fig. 7.16(a). The It2 value of the design with source pumping resistance was significantly higher than that without source pumping resistance. The It2 values of the designs with and without source pumping resistance are about 3.14 A and 2.26 A

under VDD1-to-VSS2 TLP stresses, respectively. On the other hand, the other TLP measured results, which the cross-power-domain ESD protection designs were adopted as GC-PMOS and GC-NMOS transistors, with the different source pumping resistances of 5 Ω and 15 Ω were also shown in Fig. 7.16(b).

(a)

(b)

Fig. 7.15. (a) The 100-ns TLP measured I-V characteristics of the cross-power-domain ESD protection design with GC-PMOS and GC-NMOS transistors under VDD1-to-VSS1, VSS1-to-VSS2, and VSS2-to-VDD2 three different stress combinations. (b) The 100-ns TLP measured I-V characteristics of the three different cross-power-domain ESD protection designs under VDD1-to-VSS2 stresses.

The It2 values were increased by increasing the resistance of the source pumping resistors. According to the measured results, the source pumping resistance can be expected to enhance the ESD robustness for the cross-power-domain ESD protection designs. However, this source pumping resistances would also cause the body effect and affect the circuit performance on the receiver.

(a)

(b)

Fig. 7.16. The influence of source pumping mechanism on the TLP measured I-V characteristics of the cross-power-domain ESD protection designs under VDD1-to-VSS2 stresses. (a) With or without source pumping resistance in the design with GCT NMOS transistor. (b) With source pumping resistance of 5 Ω or 15 Ω in the design with GC-PMOS and GC-NMOS transistors.

Table 7.2

HBM and MM ESD Robustness of the Different Cross-Power-Domain ESD Protection Designs under VDD1-to-VSS2 and VDD1-to-VDD2 ESD Testing Conditions

7.3.3. Failure Analysis and Discussion

The cross-power-domain ESD protection design with diodes presented lower ESD robustness among all ESD testing conditions, shown in Table 7.2. However, the lower ESD robustness of the ESD protection design with diodes can be attributed to two completely different failure mechanisms under VDD1-toVSS2 and VDD1-to-VDD2 ESD stresses, respectively. First, the failure spot of the design with diodes was located at the source side of the driver’s PMOS transistor under VDD1-to-VSS2 ESD stresses, as shown in Figs. 7.17(a) and 7.17(b). This failure spot only occurred on the source side of the driver’s PMOS transistor. The gate area and drain side of the driver’s PMOS transistor did not be destroyed after VDD1-to-VSS2 ESD stresses, as illustrated in Fig. 7.17(b). The failure mechanism could be explained that the vertical pnp bipolar transistor was turned on to cause the serious contact spike on the source side, as shown in Figs. 7.17(b) and 7.17(c). This vertical pnp bipolar transistor consisted of the P+ source diffusion of the driver’s PMOS, the N-well, and the mutual P-substrate, as shown in Fig. 7.17(c). Furthermore, this vertical pnp bipolar transistor would easily incorporate with a lateral npn bipolar transistor, which consists of the n-well, the p-substrate, and the N+ source diffusion of the driver’s NMOS to construct a parasitic SCR path between VDD1 and VSS1, as also illustrated in Fig. 7.17(c).

(a) (b)

(c)

Fig. 7.17. (a) After VDD1-to-VSS2 HBM ESD stress, the failure spots of the cross-power-domain ESD protection design with diodes were located at the source side of the driver’s PMOS transistor (Mp1). (b) The zoomed-in view of the failure spot. (c) The failure mechanism of the cross-power-domain ESD protection design with diodes under VDD1-toVSS2 HBM ESD stress.

Fig. 7.17. (a) After VDD1-to-VSS2 HBM ESD stress, the failure spots of the cross-power-domain ESD protection design with diodes were located at the source side of the driver’s PMOS transistor (Mp1). (b) The zoomed-in view of the failure spot. (c) The failure mechanism of the cross-power-domain ESD protection design with diodes under VDD1-toVSS2 HBM ESD stress.