Chapter 3 Phase Lock Loop Theory and System Simulation
4.4 Charge Pump
The ability of the charge pump is to charge or discharge the energy of the loop filter.
When the phase and frequency detector gives the charge signal (UP), the charge pump would charge the loop filter in order to raise the control voltage of the oscillator. That would increase the oscillation frequency of VCO. On the other hand, it would discharge it to lower the control voltage. The main design key is to increase the matching between the charge and discharge current. This is because the difference between charge and discharge current would generate some residue current during the compared cycle period of PFD. The residue current would cause the variation of control voltage periodically. That makes the output of the frequency synthesizer generating the reference spur seriously. The other design key is to ensure the stability of the charge and discharge current to be identical, so there would not have the over charging or over discharging cases. The detailed contents of charge would be presented in the following.
4.4.1 Operational Principle
A PFD couldn’t alone provide the exact voltage (or current) signal proportional to the phase difference at its inputs. A charge pump serves to convert the difference of the two output signal UP and DN of the PFD into the corresponding error current either sourced to or sunk from the loop filter, depending on the state of the switches SU and SD controlled by UP and DN, respectively. No current flows through the loop filter if both switches are off and the output node represents an infinite-impedance towards the loop filter.
A charge pump (CP) with a PFD and a capacity CP as the loop filter is shown in fig 4.31, which illustrates the corresponding time-domain response. One should note that the system is
nonlinear and discrete time in the strict sense. To overcome this quandary, it could be approximated by a continuous-time model only when the loop bandwidth is much less than the reference frequency [35]. Therefore, the characteristic of the PFD and charge pump can be together approximated linearly as:
e P 2
I I θ
π
= ⋅Δ
(4-10) where Ie is the average error current over a cycle, Δθ represents the phase error between the PFD inputs and IP = I1 =I2 is the current value of the two current sources in the charge pump.
Figure 4.31 The block diagram of the PFD and charge pump with the timing diagrams.
4.4.2 Design Consideration [36]
Because of the effect of the channel length modulation, the charge current I and up discharge current Idown of the conventional current-steering charge pump circuit could not match in whole range of the oscillator control voltage. Even if the PMOS and NMOS of the output stage in charge pump are sizing as the rate of their mobility ratio and the same over-drive voltage, they still cannot fit in with the total control voltage range. At every reference clock edges, the I and up Idown would both turn on for a very short time to cancel
the dead zone effect of the PFD. If the I and up Idown are not equal at this moment, the mismatch current will increase the spur level of the oscillator output spectrum.
Loop filter
Figure 4.32 The current-match charge pump architecture used in this work
Fig 4.32 upon shows the current-match charge pump circuit which has a function could let the I and up Idown tally with each other. The right part of fig 4.32 is the charge pump core circuit, and the left part is the replica bias circuit. This replica circuit is used to give the transistors M12 and M13 the same bias as M10 and M11. The replica bias circuit has a feedback loop which could tune the I fit in with the up Idown automatically while the output of the charge pump is varying.
(a)
(b)
Figure 4.33 (a) The feedback loop of the charge pump, and (b) the equivalent circuit of the loop
Fig 4.33 (a) above shows the half circuit of Fig 4.32. The error amplifier and the other transistors form a negative feedback loop and we could view the error amplifier as the first stage. M17 is the amplifier of the second stage, and M18 in the triode region series connects with M19 in diode connection. The third stage is a common-source amplifier M13 with the output load r //o12 r . The negative feedback would be equivalent to a unit gain buffer as fig o13 4.33 (b) upon. This would be a voltage follower buffer that the Vtrace would trace the V c voltage. The gain of the feedback loop would be analyzed as follows.
The gain of the error amplifier is A (negative value), and then the gain of the second err stage, CS amplifier, is shown below:
19
gm are the equivalent resistance of M18 in triode region and M19 in diode connection respectively.
The third stage of the loop is also a CS amplifier whose gain is as follow:
⋅ Then, the overall gain of the negative feedback loop is as:
⋅ ⋅
And the channel length modulation effect coefficient is λ, the maximum ⎟ could calculate the maximum mismatch of the charge and discharge current:
( ) (
up down)
The higher loop gain of the negative feedback is, the smaller current mismatch ratio is.4.4.3 Circuit Realization [36]
There is a serious problem might happen in current-match charge pump which is shown in fig 4.32. The output of the error amplifier is a high impedance node that when supply voltage grows like a ramp of time and takes long time to reach VDD, the V might be pulled c up to approach VDD. And the V would be out of the input range of the error amplifier, the c error amplifier turns off. Therefore, the discharge part of the charge pump would disable and Idown becomes zero. PLL would fail to have correct function, and the output frequency would always keep low.
The proposed current-match charge pump is shown in fig 4.34 below. The added transistors M21 and M22 would give the discharge part of the charge pump a constant bias. It could suppress the V going to near c VDD, and the charge pump would never fail to function in low frequency.
Loop filter
Figure 4.34 The proposed current-match charge pump with solved start-up problem
Because the gain of proposed two-stage voltage control oscillator is negative, the UP/DN signals are connected to the inputs reversely. To increase the output frequency of the oscillator, the control voltage V should sink to zero. And the output frequency would be decreased that c if the VDD is charging the control line of the oscillator.
The simulated results of the charge pump combined with the phase and frequency detector is shown as follows. In fig 4.35 (a) and (b), the control line of the oscillator is charge toward VDD in case of the divided signal leading to reference signal and the charging current is around 50 μA. On the other hand, the control voltage of the oscillator is sinking toward 0V in case of the divided signal lagging to reference signal which is shown in fig 4.36 (a) and (b), and the discharging current is also around 50 μA in the simulated waveforms. The average
current consumption of the charge pump is 0.72 mA, and the power consumption is 0.87 mW in the simulated results.
Reference signal Divided
signal
Down signal Up signal
Discharge current
Charge current
Reference frequency < divided frequency
== charge
50 μA
(a)
(b)
Figure 4.35 (a) The simulation results of the proposed PFD and charge pump, and (b) the control line of the oscillator in charging case
(a)
(b)
Figure 4.36 (a) The simulation results of the proposed PFD and charge pump, and (b) the control line of the oscillator in discharging case
The mismatching ratio of the charging and discharging current under the control voltage range is shown in fig 4.37. As the result, the mismatching of the charge pump would less than 4% under the oscillator control voltage 0.1~1.1V.
Mismatch < 4%
Current mismatch (%)
Control voltage (V)
Figure 4.37 The mismatching ratio of the charge pump between charging and discharging currents
The summary and the comparison of the proposed charge pump is shown in the Table 4.3 below.
Table 4.3 The summary and comparison of the CP for the important characteristics
This Work [41] [42]
Maximum
frequency Up to 1 GHz Up to 0.5 GHz Up to 1 GHz Ref Current 50 uA 10 uA 10 uA
Power 0.87 mW 60 uW ~28 uW
Supply Voltage 1.2 V 1 V 1 V
Technology CMOS 0.13μm
CMOS 0.18μm
CMOS 0.18μm