Phase and Frequency Detector

The phase and frequency detector (PFD) could detect the difference of the phase and frequency between the input reference frequency and the divided frequency. It mainly detects the phase differences for the charge pump to revise the output frequency of the oscillator, so it could also be called phase detector, PD. The followings are the operational principle of the conventional phase and frequency detector we utilized.

4.3.1 Operational Principle

Nowadays, the common phase detectors can be categorized to three types: the analog multiplier-type, the XOR-type, the sequential-type. However, the analog multiplier-type phase detector exhibits the nonlinear dependence of the output voltage on the phase difference and the instability, resulting from the inverted gain polarity beyond the phase difference range, ± π/2. Concerning the XOR-type phase detector, the instability issue still exists except for the nonlinear dependence.

Unlike the multiplier-type and XOR-type, which are only phase-sensitive, the phase-frequency detector (PFD) is a sequential phase detector triggered by else the rise or fall edge of the reference signal and the divided signal. As the result, the PFD has the capability of operating as a frequency discriminator for large frequency errors or as a coherent phase detector once inside the pull-in range of the PLL, allowing a fast frequency acquisition and a full linear phase difference range, ± 2π shown in fig 4.25 below.

Figure 4.25 The characteristic of the phase and frequency detector

As illustrated in fig 4.26 below, the operation of a typical PFD is as follows. If initially UP = DN = 0, then a rising transition on reference frequency leads to UP = 1, DN remains 0.

The circuit remains in this state until the divided frequency goes high, upon which UP returns to zero simultaneously. The behavior is similar for the divided signal input. Thus, the average dc value of (UP-DN) is an indication of the frequency or phase difference between reference signal and divided signal.

Figure 4.26 The conceptual operation of phase and frequency detector

To achieve a PFD with the above behavior, at least, three logical states are required: UP

= DN = 0 (state 0); UP = 1, DN = 0 (state I); UP = 0, DN = 1 (state II). Fig 4.27 below shows a state diagram summarizing the operations. If the PFD is in the state 0, then a transition on reference signal takes it to state I. During state I, any more rising edge on reference signal would not changes the state at all. The PFD will remain in this state until a transition occurs on divided signal, upon which the PFD returns to state 0 immediately. The switching sequence between state 0 and state II is similar. Such a PFD is called “tri-state phase-frequency detector”.

Figure 4.27 The state diagram of the tri-state phase and frequency detector

4.3.2 Design Consideration

Figure 4.28 The structure of the tri-state phase and frequency detector

Fig 4.28 upon is the structure of the tri-state phase and frequency detector. It includes two edge-triggered, resettable D-type flip-flops (DFFs), a delay chain, and an NAND gate.

Note that the use of the edge-triggered DFFs is to avoid the dependence of the output upon the duty cycle of the inputs.

The D inputs of the flip-flops are tied to logic one (VDD). Reference signal and divided signal act as the clock inputs of the two DFFs, respectively. A positive transition in the input of the reference signal sets the output UP “high”. Similarly, a positive transition in the input of the divided signal sets the output DN “high”. When both UP and DN are simultaneously

“high”, a reset pulse generated by the NAND gate and inverter chain as “AND” resets both flip-flops, which brings UP and DN to low and then terminates the reset pulse. In order to eliminate the dead-zone, a delay chain has been introduced in the reset path, so that minimum

width pulses are always present in the outputs UP and DN when the inputs are in phase. That would increase the response time for charge pump to minimize the influence of the reference spurs.

The circuit architecture of the D-type flip-flops in the proposed phase and frequency detector is shown in fig 4.29 below. It is a true single phase circuit (TSPC) structure that could increase the linearity, decrease the switching time, and has simple circuit structure.

Figure 4.29 The structure of the TSPC D-type flip-flop in phase and frequency detector

4.3.3 Design Consideration

Fig 4.30 shown below is the simulation results of the phase and frequency detector. Fig 4.30 (a) is the simulated waveform of the divided frequency leading to the reference frequency, thus the PFD would generates the discharging signal for the charge pump to lower the control voltage of the oscillator. That would let the oscillation frequency decrease and then reduce the divided frequency. On the other hand, fig 4.30 (b) is the simulated waveform of the divided frequency lagging reference frequency. The PFD would generate the discharging

signal for the charge pump to raise the control voltage of the oscillator. That would let the oscillation frequency increase proceed to heighten the divided frequency. The average power consumption of the proposed phase and frequency detector is about 0.2 mW. The phase characteristic (linear range) at 100 MHz is ±2π , and at 500 MHz is ±1.65π. These are presented in Table 4.2 shown below.

(a) (b)

Figure 4.30 The simulated waveform of phase and frequency detector at (a) divided frequency leading to reference frequency, and (b) divided frequency lagging reference frequency

Table 4.2 The summary and comparison of the PFD for the important characteristics

[33] [34] This Work

Maximum Frequency 1.53 GHz 1.7 GHz 500 MHz

Power ~1.4 mW ~4.5 mW 0.2 mW (ave)

Phase Characteristic (Linear range)

@0.1GHz none ± 2π ± 2π

@0.5GHz ± 1.8π none ± 1.65π

@ 1 GHz none ± 1.3π none

Technology CMOS 0.25 μm CMOS 0.18 μm CMOS 0.13 μm REF

DIV UP DN

REF DIV UP DN