Circuit Realization

Figure 4.10 The circuit diagram of the proposed two-stage ring oscillator and the oscillator buffers

Fig 4.10 is the final version of the differential delay cell of the proposed two-stage ring oscillator and the buffers of the oscillator. The M1, M3, M4, and M6 also form a differential amplifier; the M2 and M5 is the regeneration latch as the positive feedback either. The current source is taken for the high output amplitude. We add another PMOS load as control transistor by changing the gate voltage to vary the oscillation frequency. The operational principle is the same as the discussion in the previous section we presented and it could make the better performance. The ring oscillator buffer is designed as common source amplifiers composing of transistors Mb1~Mb4 and resistors R1~R4 [37].

We first design the differential delay cell satisfying the requirement in previous section.

The most important condition is that when the phase shift changes absolutely 90º in frequency response, the gain should be greater than 0dB. The result of the proposed differential delay cell is shown in fig 4.11 below.

Figure 4.11 The frequency response of the proposed differential delay cell

The second step is to verify if the changes in one input phase must let the both two output phase change. We would easily find out that even if there is only one disturbance in one input of the differential delay cell, both the outputs of the differential delay cell which satisfy the first demand and has the regeneration latch would fit the second requirement. The stronger the positive feedback is, the faster response happened in the differential outputs. Fig 4.12 below is the input and output signals of the proposed differential delay cell. We only input a sine wave signal to the V , and the _i+ V is a common mode voltage. Both the _i− differential outputs would have the differential signals.

Figure 4.12 The input and output signals in differential delay cell with only one input signal.

The verification of the differential delay cell would make sure that the ring oscillator would oscillate or not. The other conditions of the differential delay cell would let the ring oscillator has better performance. We could design it as a reference.

The ring oscillator we need to operate in phase lock loop should output the signal for the architecture of the UWB frequency synthesizer. The output frequency of this PLL is 7128 MHz. That means the central frequency of the voltage control ring oscillator should be 7128 MHz. The intervals between the central frequency and the upper and lower operation frequency set up at least 1 GHz bandwidth. And let the central frequency in linear range of the VCO gain.

The MOS device size of the cross couple pair, regeneration latch would affect the oscillation frequency. The smaller device size of the latch is, the weaker locking ability to the differential output frequency is. That would let the differential output signals change their voltage states easier and faster, and the oscillation frequency goes higher. However, if the regeneration coupling ability is not powerful enough, the phase variation in single input

cannot transfer to the phase response in differential outputs. We estimate that the output loading of the ring oscillator buffers would be smaller than 100fF, so we put a 100fF capacitance in the output of each stage of the differential delay cell. That contains the wire loading and the loading of PADs.

The transient situation in output of the ring oscillator at 7128 MHz is shown in Fig 4.13 below. The common mode voltage is 0.6979 V, and the amplitude of the output signal is 0.4459 V.

Figure 4.13 The transient results of the ring oscillator at 7128 MHz

Simulation results as shown in fig 4.14 are the phase noise of the two-stage voltage controlled ring oscillator at 7128 MHz. The VCO with loop filter phase noise is -116.9dBc/Hz at 1MHz frequency offset. It is adequately satisfying the specification of the UWB application, -96.5 dBc/Hz at 1 MHz frequency offset.

rin Figure 4.14 The phase noise of the two-stage g oscillator

Fig 4.15 below shows the output frequency tuning range, which is from 5.8 GHz to 8.8 GHz. For the designed frequency band, the average gain of VCO is about -4.43 GHz/V. The current consumption of the two-stage voltage control oscillator is 10.35mA, thus its power consumption is 12.42mW. And the current consumption of the two output buffers is 8.49mA, and the power consumption is 10.19mW.

Figure 4.15 The tuning range of the two-stage ring oscillator

The output power spectrum of the two-stage voltage controlled ring oscillator is shown in fig 4.16 below.

Figure 4.16 The output spectrum of the two-stage ring oscillator

Finally, the verification of the process variation would be considered. The sensitivity of the two-stage ring oscillator under FF and SS corners is depicted in fig 4.17. Both of the FF and SS corner could oscillate and they also cover the 7128 MHz.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Figure 4.17 The tuning range of the two-stage ring oscillator at 7128 MHz under TT, FF and SS corner

The summary and comparison of the proposed two-stage voltage control ring oscillator is shown in Table 4.1 below.

Table 4.1 The summary and comparison of the proposed oscillator

This work [25]

Architecture Ring Ring Ring Ring

Output phase quadrature quadrature quadrature quadrature Tuning range (GHz) 5.8~8.8 0.2~2.1 8.4~10.1 1.05~1.45

Supply Voltage 1.2 V 3.3 V 1.8 V 1.2 V

DC Power (mW) 12.42 7.01 100 8.58

Phase noise (dBc/Hz) -117.6@1MHz -90@0.1MHz -99.9@1MHz -88@1MHz

KVCO (GHz/V) -4.43 1 1.13 0.38