Chapter 3 Phase Lock Loop Theory and System Simulation
3.3 PLL System Simulation
3.3.2 System Simulation
The system simulation procedure mainly divides into four parts: 1. the design of the KVCO, 2. the decision of the charge pump current, 3. the design of the loop bandwidth, and 4.
the design of loop filter. In this section, we would set up the system simulation step by step as follows:
The design of the KVCO
The first step of system simulation for PLL is to set up a modeled VCO for the future used. This VCO does not the final version of the PLL, but it supports us to understand the behavior and the data of VCO. The most important issue of this is the gain of VCO, it is one of the loop gain factor in PLL. This procedure also needs to construct the phase noise model of VCO. Because of the noise sources from other than the reference oscillator and VCO are usually relatively insignificant and hence negligible. In other words, the overall phase noise performance is mostly dominated by the reference oscillator and VCO. However, the reference frequency in this work would be produced by the signal generator outside the chip.
VCO noise behavior is the most critical point in the PLL system. From the noise behavior of VCO, we could establish the noise environment to design the other properties.
The details of the design considerations and simulation procedures would be completely discussed in the next chapter. This design of VCO is only the rough simulation in order to
gain the data we need. Therefore, the rough simulation of VCO would not present here instead of the simulated data from transistor level. The most important data we need is the VCO gain KVCO. The VCO gain in this work is 8.8 GHz/Volt, and the phase noise performance is in fig 3.9 below.
Figure 3.9 Phase noise performance of roughly simulated VCO
The quantity of phase noise could be modeled by an linear line
( ) [ ( ) ( ) ]
It would replace the real noise behavior in the PLL system simulation in Simulink. That makes the outcome of the system simulation more accurate than tradition method. The tradition method is using analytic equation [19] as:2 3
Then substitute the parameter as the TSMC 0.13μm process’ model characteristic.
However, the equation would not be more correct than using the simulation software tools.
The detailed analysis would also be presented in the next chapter.
The decision of the charge pump current
Charge pump current in the PLL is also an important issue. How to choose a correct value of charge pump current affects the reliability and the noise performance. The more charge pump current PLL uses, the more noise would be suppressed. However, it would cause the reliability problem and the increasing power consumption. The better way is to let the charge pump current slightly over the current that just make the phase noise of PLL matching the specification and cost the least power consumption. In order to achieve the goal, we would construct the phase noise simulation environment for the PLL.
The phase noise similar model of VCO is mentioned above, and the phase noise caused by divider and reference is tiny. The noise of charge pump and loop filter would be concerned.
Fig 3.10 below is the equalized structure of the charge pump and the loop filter. The loop filter is 2nd order structure as we mentioned in the previous section. Due to the negative VCO gain, the UP and DOWN signals of the charge pump are reverse to each other from typical signals.
VDD
Figure 3.10 The equalized structure of charge pump and loop filter
We can know that the main noise sources of charge pump come from the up/down tail current source from fig 3.10. The current sources are always constructed of NMOS and PMOS. As the result, the two transistors would become the main noise source. Referring to National Semiconductor, we could get the noise mentioned as:
p Where the 4KTgm is the noise of channel resistance, and the
p
is the flicker noise of NOMS and PMOS respectively.
The noise source of loop filter mainly comes from the hot noise of resistor as:
2
Finally, we can consider the noise of charge pump and loop filter together with current From equation 3-12, and 3-16, we can understand the phase noise of VCO, charge pump, and the loop filter. And we analyze the transfer function of every noise source. The influence quantity at the output of PLL could be gained by multiplying the noise quantity and its transfer function. The whole data could be put into the PLL noise simulation model by Matlab to set up a noise simulation environment to get the specification we need. Fig 3.11 shows the output phase noise with different charge pump current.
2 3 4 5 6
The optimized charge pump current is 50μA
Figure 3.11 The variation of output phase noise with different charge pump current
The arrow tip means the trend of decreasing the charge pump current. We could find out
that the bigger charge pump current is, the lower output phase noise is. The final decision is to choose the current that satisfy the PLL system specification and not to cost too much power consumption. 50μA is the best choice for this consideration as charge pump current.
The decision of the loop bandwidth
The loop bandwidth affects the performance of settling time and output phase noise. It also has huge influence in reliability issue. There is trade-off between settling time and the ripple on the VCO control line. The lower loop bandwidth is; the greater suppression would be the high frequency components produced by the phase frequency detector but the longer settling time. Comparatively, the lower loop bandwidth is, the shorter settling time of PLL is.
How to choose exact value for loop bandwidth is a great challenge. Fortunately, the settling issue is not the concerned problem in our UWB frequency synthesizer architecture. Because even using the fastest settling time PLL in the world cannot satisfy the specification of settling time for UWB frequency synthesizer, 9.47ns. In order to match the switching problem, it is the only way to undertake the frequency generation scheme so far. The methods in operation are illustrated in the chapter 1.
Therefore, the only issue we need to concern is to improve the output phase noise performance. In general, the loop bandwidth is at least 10 times less than reference frequency by experience. Although the lower bandwidth brings the advantage of good suppression at VCO control line, too small bandwidth causes the huge value of the passive component. For future integration, a reasonable bandwidth let the clean VCO input and acceptable value of capacitance. We choose the loop bandwidth as 3 MHz let the passive component might be integrated on chip.
The design of the loop filter
As we mentioned above about the loop bandwidth, it affects not only the settling time and output phase noise but the reliability. The choice of the loop bandwidth causes the variation of the phase margin. The higher loop bandwidth is, the lower phase margin of PLL is.
The phase margin issue would directly decide the value of passive component in loop filter.
By the equation of the loop gain of PLL below [20], we could figure that out.
P
equals the gain of phase frequency detector and charge pump. The k is the equivalent transfer gain of the lop filter.
By the analysis of the previous section, we would use the second order loop filter for our frequency synthesizer. Fig 3.12 below is the circuit architecture of the loop filter.
Figure 3.12 The circuit architecture of loop filter.
The loop filter would produce two poles and one zero. The first pole is at DC, the other pole and the zero would place at the right side and left side of the loop gain frequency 3 MHz respectively. The loop gain should be in the middle between the zero and the second pole. The
open-loop Bode plot is shown in Fig 3.13 below.
Figure 3.13 The open loop Bode plot of PLL.
In order to attain the phase margin 60°, we choose the zero frequency as 0.75 MHz and the second pole frequency with 12 MHz by the experienced rule, = =16
Z
b P
ω
ω as 60° phase
margin. The transfer function of the loop filter is as:
b
The loop bandwidth ωc is at the maximum phase of the phase response as:
τ = ω , the passive component values of loop filter are:
2 previously as Table 3.2 below. The passive component of loop filter would be presented.
Therefore, the loop filter analysis is finished. The value of R1 is 30.98 kΩ. C1 is 6.85 pF.
And the C2 is 0.457 pF. The analysis of loop filter could be done like this, however, there is one useful software produced by the National Semiconductor Corporation. It could analysis the loop filter directly and be more accurately. The result is shown in Fig 3.14 below. Fig 3.15 is the Bode plot of the loop filter designed by it.
Table 3.2 The parameters for analyzing the loop filter
parameter value
Charge pump current IP 50 μA VCO gain KVCO -8.8 GHz/Volt Division number N 108 Loop bandwidth ωc 3 MHz
Phase margin PM 60°
Zero frequency ω Z 0.75 MHz 2nd pole frequency ω P 12 MHz Frequency coefficient b 16
Figure 3.14 PLL loop filter design by the software
Figure 3.15 The Bode plot of the PLL designed by the software
From the software, NS filter design, the value of R1 is 4.87 kΩ. C1 is 49.18 pF, and the C2 is 2.54 pF. We set the phase margin as 65° to gain some margin. The first choice of the loop filter we decided is the second combination of the passive component for the low pass filter. The final parameters of the PLL in this work are summarized in Table 3.3 below.
Table 3.3 The final parameters of the PLL in this work
Final PLL parameters in this work
VCO gain KVCO 8.8 GHz/V
Open loop gain bandwidth ωc 3 MHz
Phase margin PM 60º
Zero frequency ω Z 0.75 MHz
Pole frequency ω P 12 MHz
Passive elements
R1 4.87 KΩ
C1 49.18 pF
C2 2.54 pF
3.3.3 Switching Time and Reliability of PLL
There are still two important verifications for the system simulation of the PLL. It is the switching time (settling time or locking time) and reliability issue in the PLL transient state and frequency response. Although the switching time is not the critical issue for our UWB frequency synthesizer architecture (the settling time in the PLL), we also need to prove and verify it. The settling time under 9.47ns of the PLL is impossible and using only one PLL to achieve the UWB frequency synthesizer is to fish in the air.
We set up the transient state behavior for the each component of the PLL with the Matlab tool, Simulink. That constructs the PLL block circuit with similar mathematical behavior model. Because of the tremendous amount of gate counts in a frequency synthesizer (especially in the frequency divider), closed-loop simulation at the gate-level will take a lot of times. Hence, some prior architecture simulations must be done with Simulink in order to achieve a well-defined closed-loop behavior (system level). A behavior model for the complete PLL is implemented in Simulink as shown in fig 3.16 below.
Figure 3.16 The PLL behavior model by Simulink
The transient simulation of the behavior model is shown in fig 3.17 below. It is the switching time from initial state to the stable state of 7128 MHz output. The settling time within 1 KHz accuracy is 41.5 μs. It exceeds the specification for the UWB frequency synthesizer very much. Therefore, using special architecture instead of single PLL is indeed a strong demand for the system to fit in with the switching time less than 9.47ns.
Figure 3.17 The locking time of the PLL from initial state to the output wanted frequency
The sensitivity of the PLL system is quite important. We set the phase margin as 60º, but the loop filter design is modeled as 65º. Reliability would affect directly the stable state of the PLL transient behavior. An unstable PLL system would never output a stable frequency spectrum because the reliability is not concerned enough. We use Matlab to verify the reliability of the PLL whose passive component of filter is design by the National Semiconductor’s software. As shown in fig 3.18 below, it could satisfy the specification of 60 degrees.
Figure 3.18 The Bode Plot of the open loop transfer function
The variation of the passive components especially the resistor would cause the unstable state because of the process variation. The worst case is the resistor varying ±30% value and might cause the phase margin decreasing. We use Matlab to model the phenomenon of that and verify that they all satisfy the specification of the 60 degrees. As shown in fig 3.19 (a), (b), it could conform to the specification we instituted. Therefore, we could make sure that the PLL system would be stable even under the process variation.
(a)
(b)
Figure 3.19 The Bode Plot of the open loop transfer function with (a) +30% (b) -30% variations
Chapter 4
Quadrature Oscillator based PLL
We have introduced the system level of PLL-based Frequency Synthesizer in Chapter 2.
In this chapter, we will demonstrate the design of individual building blocks. A PLL structure is the core of our frequency synthesizer design, which involves the designer’s analog and digital expertise. Also, it has many design constraints, some of which have been briefly stated earlier. In this chapter, we will utilize a full-custom design flow for the PLL design. The behavior simulation run by Matlab Simulink has implied the specification and direction for the system design in Chapter 3. However, the circuit level design is based on the deep submicron CMOS 0.13-μm technology. In this thesis, our focus is on the integer-N architecture.
Fig 4.1 below shows the architecture of integer-N frequency synthesizer in this thesis. It has five building blocks, including voltage-controlled oscillator (VCO), prescaler (divide by 2) and dividers (one divide by 2, three divide by 3), phase-frequency detector (PFD), charge pump (CP) and loop filter (LF). The following sections will discuss the design consideration and implementation of individual building blocks in PLL. Finally, the implementation of a complete frequency synthesizer with our proposed two-stage ring oscillator is achieved. With the help of ADS (Advanced Design System) and SPICE simulation, the results are provided in the later sections.
Figure 4.1 The architecture of the integer-N PLL in this work
4.1 Quadrature Voltage-Controlled Oscillator
Quadrature phases of every LO signal are required in UWB systems, which utilize a large bandwidth from 3.1 to 10.6 GHz. Therefore, how to provide the LO signals with quadrature phases as correct down/up conversion for receiver/transmitter are essential and critical. A LO signal with poor phase noise performance results in unwanted frequency translation of nearby interferers, degrading the receiving signal quality seriously. It is interesting to note that unlike narrowband RF systems, UWB applications exhibit susceptibility to phase noise primarily in the form of the corruption of the signal constellation.
And the effect of the reciprocal mixing is much less, pronounced because it is determined by the phase noise at an offset of several hundred megahertz. Hence, what is influenced occupies a small portion of the channel.
The proposed two-stage ring oscillator is designed to provide one of the required LO signal for the UWB frequency synthesizer with moderate phase noise performance and power consumption. And it supports the output signal for the basic phase lock loop to generate the
stable LO signal source.
4.1.1 Operational Principle [21]
In general, it has better phase noise performance by using LC tank voltage control oscillator in single chip integrated circuits. However, it must to employ passive component, spiral inductors which would consume a lot of chip area. It is also difficult to model the behavior of passive inductors exactly by simulation tools, so the taped out measurement results may have huge differences between simulations and the actual performance.
Nowadays, the ring oscillators have acceptable performance in phase noise behavior, and the spiral inductors would not be the necessary in the ring oscillator architecture. It could successfully save the space in the chip area and have wider frequency tuning range. Moreover, it is highly integrated in mixed signal ICs. Because of these advantages, it is popularly used in the early microprocessor clock generator of low frequency spectrum. By the chip process goes progress, the ring oscillator start to be utilized in constant angular velocity phase lock loop of the high frequency clock generation, giga-bit microprocessor, and DVD/CD-ROM, etc……..
The architecture of ring oscillator is like fig 4.2 below. The inverters in ring oscillators could be (a) single-ended or (b) differential output. It becomes the ring structure by connecting the output of the last stage to the input of the first stage in multi-inverters. In integrated circuits, the differential pair is much more used because of its differential signal output.
(a) (b)
Figure 4.2 The architecture of the (a) single ended (b) differential output ring oscillators.
By Barkhousen Criterion, the oscillator is a positive feedback that the closed loop gain equals 1 and the phase shift of the loop is 2nπ, (n could be any integer). If we consider an odd number of the stages inverter based ring oscillator, every stage provides basic 180° phase shift.
And the phase shift caused by the output load R and the inner/outer parasitic capacitor C also should be thought over to achieve the left phase shift. For example, the 3-stage inverter basically provide phase shift as 3×180°=540°. We want to obtain the 2nπ=720° most nearest 540°, so each stage should supply extra phase shift,
(
720°−540°)
3=60°. The RC delay time is shown as t , and the delay of n stages is d2
Ntd =T ( T is the cycle time of the
loop). Therefore, the oscillation frequency is 1 2Ntd .
If we use the even number of the stages ring oscillator as the fig 4.3 below, the differential output of the last stage would be cross back to the input of the first stage. It forms a eight-stage inverter chain equaled 2n, and the inverter loop basically provides the phase shift as 180°×8=8π. In order to obtain the positive feedback to the phase shift 2nπ, the left phase shift would share the 2π degrees to the eight inverter stages. That means the delay time of each stage is t , and the d 2Ntd =T . Therefore the oscillation frequency is:
d
osc Nt
f 2
= 1 .
(4-1)
Figure 4.3 The architecture of the even number stages ring oscillator with RC equivalent delay.
The inverter gain and the phase shift of each inverter stage would be considered in the next step. We simply assume by first order approximate that each inverter stage contains a dominant pole formed by the load R and parasitic C. The transfer function of each inverter stage would be: The whole loop transfer function of the 3-stage inverter chain ring oscillator would be:
( )
3 3 The 3-stage inverter should support 180° for the loop to attain the 2nπ=720°, so each stage should provide the phase shift, 60°. In Bode plot, the equation of the frequency response in phase is as:
°
=
− 60
tan 1
o osc
ω ω
(4-4) Therefore, the ωosc = 3ωo, and ωosc substitute into the equation 4-2. The loop gain should be greater than 1, so the smallest gain of each inverter stage would be Ao ≥2.
By the same analysis, each inverter stage of the 4-stage differential ring oscillator would
By the same analysis, each inverter stage of the 4-stage differential ring oscillator would