Chapter 3 Phase Lock Loop Theory and System Simulation
4.7 Summary of the 3168-MHz PLL
As the system simulation and circuit design flow we set up in the previous chapter and section, the second PLL which outputs 3168-MHz in the proposed frequency generation scheme could be designed simply. Some of the dividers, the phase and frequency detector and charge pump use the same circuits as the 7128-MHz PLL. The summary of the proposed 3168-MHz PLL is listed in the Table 4.6 below. Table 4.7 is the summary and the
comparisons of the proposed two PLLs.
Table 4.6 The summary of the 3168-MHz PLL
Parameter Simulation result
Output frequency (MHz) 3168
Reference frequency (MHz) 66
Spur rejection (dBc) -55
Division number 48
Settling time (μs) 32.2
Total dc power (mW) ~15.5
Process TSMC 0.13 μm
Two-stage ring oscillator
Tuning range (GHz) 2.6~3.8 Phase noise (dBc/Hz) -105.2@1MHz
Phase error (°) 0.25
DC power (mW) 3.30
VCO buffers DC power (mW) 8.49
Dividers DC power (mW) 1.88
Phase and frequency detector
Linear range @ 0.1GHz ± 1.8π
DC power (mW) 0.2
Current-match charge pump
Mismatching ratio < 4%
Maximum frequency (GHz) 1
DC power (mW) 0.87
Loop filter order 2nd
Phase margin (°) > 60
Table 4.7 The summary and comparisons of the proposed two PLLs
quadrature quadrature quadrature differential differential Three quadrature
Central
117@1MHz 105@1MHz 115@1MHz 104@1MHz 81@0.1MHz 97@1MHz 100@1MHz
Technology 0.13μm
Chapter 5 Conclusion and Future Work
5.1 Conclusions
A 1.2-V phase lock loop with two-stage voltage control oscillator and current-match charge pump for full-band UWB frequency synthesizer has been designed in a TSMC 0.13-μm CMOS technology. The new frequency spectrum generation scheme is also proposed for the least usage of the SSB mixers to improve the performance of the spur level. In addition, a two-stage voltage control ring oscillator with quadrature phase output has been designed to implement a small chip area and high integration oscillator. The architecture of the proposed frequency synthesizer is the most directly perceived through the sense, and the system is the most uncomplicated to realized. There are not any inductors in our phase lock loop and it is the least number of the SSB mixers, so the chip area of the proposed frequency spectrum generation scheme would be reduced hugely.
The improved current-match charge pump is also proposed in this work. This new current-match charge pump solves the start-up problem, and it still has good performance in current matching.
Finally, a clear design flow of phase lock loop is presented in this work. By using the Matlab and Simulink, the simulation in system level could decrease the designing time of the whole phase lock loop circuits. The more accurate simulation in system level, the less modification takes in transistor level.
5.2 Future work
The proposed architecture for UWB frequency synthesizer has three blocks unfinished.
And it could be fabricated with the simulated system and complete structures. It also could be integrated with the UWB receiver done by Yi-Kai Lo to verify the capability of the frequency synthesizer for UWB applications.
References
[1] Federal Communications Commission, FCC 02-48 ET Docket 98-153
[2] Behzad Razavi, Fellow, IEEE, Turgut Aytur, Christopher Lam, Member, IEEE, Fei-Ran Yang, Member, IEEE, Kuang-Yu (Jason) Li, Member, IEEE, Ran-Hong (Ran) Yan, Han-Chang Kang, Member, IEEE, Cheng-Chung Hsu, and Chao-Cheng Lee, “A UWB CMOS Transceiver, “IEEE J. Solid-State Circuits, vol. 40, NO. 12, December, 2005 [3] Behzad Razavi1, Turgut Aytur2, Fei-Ran Yang2, Ran-Hong Yan2, Han-Chang Kang3,
Cheng-Chung Hsu3, Chao-Cheng Lee3, “A 0.13μm CMOS UWB Transceiver, “ ISSCC 2005, Session 11, ULTRA WIDEBAND SOLUTIONS, 11.9
[4] Jri Lee, Member IEEE, “A 3-to-8-GHz Fast-Hopping Frequency Synthesizer in 0.18-μ m CMOS Technology, ” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.
3, MARCH 2006
[5] Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma, “A 14-band Frequency Synthesizer for MB-OFDM UWB Application, “ ISSCC 2006, Session 6, UWB Transceivers, 6.7
[6] Zue-Der Huang, Fong-Wei Kuo, Wen-Chieh Wang and Chung-Yu Wu, “A 1.5-V 3~10-GHz 0.18-μ m CMOS Frequency Synthesizer for MB-OFDM UWB Applications,
“ Microwave Symposium Digest, 2008 IEEE MTT-S International
[7] Tai-You Lu, Wei-Zen Chen, “A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System, “ ISSCC 2008, Session 6, UWB Potpourri, 6.6
[8] Physical Layer Submission to 802.15 Task Group 3a : Multi-Band Orthogonal Frequency Division Multiplexing, IEEE P802.15-03/268r2.Per
[9] Pengbei Zhang, Mohammed Ismail, “A New RF Front-End and Frequency Synthesizer
Architecture for 3.1~10.6GHz MB-OFDM UWB Receiver, “ Circuits and Systems, 2005, 48th Midwest Symposium on
[10] Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi, and Seong Su Park, “A 6.3–9-GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications,”
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005
[11] SUMIT ROY, JEFF R. FOERSTER, V. SRINIVASA SOMAYAZULU, AND DAVE G.
LEEPER, “Ultrawideband Radio Design: The Promise of High-Speed, Short-Range Wireless Connectivity,” PROCEEDINGS OF THE IEEE, VOL. 92, NO. 2, FEBRUARY 2004
[12] Chinmaya Mishra, Student Member, IEEE, Alberto Valdes-Garcia, Student Member, IEEE, Faramarz Bahmani, Student Member, IEEE, Anuj Batra, Member, IEEE, Edgar Sánchez-Sinencio, Fellow, IEEE, and Jose Silva-Martinez, Senior Member, IEEE,
“Frequency Planning and Synthesizer Architectures for Multiband OFDM UWB Radios,
“ IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 12, DECEMBER 2005
[13] Ana García Armada, Member, IEEE, “Understanding the Effects of Phase Noise in Orthogonal Frequency Division Multiplexing (OFDM), “IEEE TRANSACTIONS ON BROADCASTING, VOL. 47, NO. 2, JUNE 2001
[14] Thieny POLLET, Mark VAN BLADE and Marc MOENECLAEY, Member, IEEE,
“BER Sensitivity of OFDM Systems to Carrier Frequency Offset and Wiener Phase Noise, “ IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995
[15] Jan Tubbax, Boris Côme, Liesbet Van der Perre, Stéphane Donnay, Marc Engels, Hugo De Man, and Marc Moonen, “Compensation of IQ Imbalance and Phase Noise in OFDM Systems, “ IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 4, NO. 3, MAY 2005
[16] F. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. Comm., vol. 28, pp.
1849-1858, Nov. 1980.
[17] Yi-Shing Shih, the thesis “Design of Low Jitter Frequency Synthesizers with Fast Frequency Acquisition Phase-Frequency Detector,” Department of Communication Engineering, National Chiao-Tung University.
[18] Dai-Yuan Yu, the thesis “A Dual Band, Quad Mode Δ-Σ Frequency Synthesizer for Direct Conversion Transmitter,” Department of Electronics Engineering, National Chiao-Tung University.
[19] D.B. Leeson “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol.
54, pp. 329-330, Feb. 1996.
[20] Behzad Razavi, “RF Microelectronics”, chapter 8, Prentice Hall, 1997.
[21] Y.H. Kao, “The phase lock loop IC design,” chapter 5, TsangHai, 2005
[22] H. Djahanshahi and C. Salama, “Robust two-stage current-controlled oscillator in sub-micrometer CMOS,” IEEE J. Solidstate circuits, vol. 35, No. 6, pp. 847-855, March 2001.
[23] E. Wang and R. Harjani, “Partial Positive Feedback for Gain Enhancement of Low-Power CMOS OTAs,” Analog Integrated Circuits and Signal Processing, 8, pp21-35, 1995.
[24] J. Maneatis and M. Horowitz, “Precise delay generation using coupled oscillators,” IEEE J. Solid-State Circuits, vol.28, No. 12, pp. 1273-1282, Dec 1993.
[25] Daniel Pacheco Bautista, Mónico Linares Aranda, “A Low Power and High Speed CMOS Voltage-controlled Ring Oscillator,” IEEE, ISCAS 2004
[26] Yun-Hsueh Chuang, Sheng-Lyang Jang, Jian-Feng Lee and Shao-Hua Lee, “A Low Voltage 900MHz Voltage Controlled Ring Oscillator with Wide Tuning Range,” The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9,2004
[27] Daniel Decle Colin, Alejandro Diaz Sanchez and Monico Linares Aranda, “Design of 2 stages ring oscillators applying local networks of feedback, “ IEEE 18th International Conference on Electronics, Communications and Computers
[28] Luciano Severino de Paula, Sergio Bampi, Eric Fabris, Altamiro Amadeu Susin, “A Wide Band CMOS Differential Voltage-Controlled Ring Oscillator, “2008 IEEE [29] Ullas Singh, Michael M. Green, “ High-Frequency CML Clock Dividers in 0.13-μm
CMOS Operating Up to 38 GHz,’ IEEE J.Solid-State Circuits, vol. 40, no8, pp1658-1661, Aug. 2005.
[30] B. Razavi et al., “Design of high speed, low power frequency divider in 0.25 μm CMOS,” IEEE J.Solid-State Circuits, vol 30, pp. 101-108, Feb. 1995.
[31] Ullas Singh, and Michael Green, “DYNAMICS AND HIGH-FREQUENCY CMOS DIVIDERS,” ISCAS 2002, vol. 5, pp. V-421-V-424, May 2002
[32] Yi-Kai Lo, the thesis “A Design of a 3.1~10.6 GHz CMOS Direct-Conversion Receiver Front–End for UWB Applications,” Department of Electronics Engineering, National Chiao-Tung University.
[33] Mozhan Mansuri, Dean Liu, and C-K K Y., “Fast Frequency Acquisition Phase
Frequency Detectors for GSamples/s PLL”, IEEE Journal of Solid-State, Vol. 37, No.10, Oct. 2002.
[34] R-Y C, H-Y H.,＂A fast-acquisition CMOS Phase/Frequency Detector.＂, Digital Object Identifier 10.1109/EIT.2006.252137 Digital Object Identifier
10.1109/EIT.2006.252137, May 2006 Page(s): 488-491
[35] F. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. Comm., vol. 28, pp.
1849-1858, Nov. 1980.
[36] Chih-Yuan Hsieh, the thesis “A 1-V 2.4-GHz CMOS Frequency Synthesizer with Current-Match Charge Pump,” Department of Electronics Engineering, National Chiao-Tung University.
[37] Hai Qi Liu, Wang Ling Goh and Liter Siek, “A 0.18-μm 10-GHz CMOS Ring Oscillator for Optical Transceivers, “ IEEE 2005.
[38] K. R. Lakshmikumar, V. Mukundagiri and S.L.J. Gierkink, “A Process and Temperature Compensated Two-Stage Ring Oscillator, “ IEEE 2007 Custom Intergrated Circuits Conference (CICC).
[39] Chung-Yu Wu, Yi-Kai Lo, and Min-Chiao Chen, “A 3.1~10.6 GHz CMOS
Direct-Conversion Receiver for UWB Applications, “ Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on.
[40] Chan Tat Fu and Howard C. Luong, “A 0.8-V CMOS Quadrature LC VCO Using Capacitive Coupling, “ IEEE Asian Solid-State Circuits Conference, November 12-14, 2007
[41] Rola A. Baki and Mourad N. El- Gamal,, “ A New CMOS Charge-Pump for
Low-Voltage High-Speed PLL Applications, ” Circuits and Systems, 2003. ISCAS '03.
Proceedings of the 2003 International Symposium on Volume 1, 25-28 May 2003 Page(s):I-657 - I-660 vol.1
[42] Hong Yu; Yasuaki Inoue; Yan Han.,”A New High-Speed Low-Voltage Charge Pump for PLL Applications, ” ASIC, 2005. ASICON 2005. 6th International Conference On
Volume 1, 24-27 Oct. 2005 Page(s):387 - 390 Digital Object Identifier 10.1109/ICASIC.2005.1611344
[43] Kari Stadius, Member, IEEE, Tapio Rapinoja, Jouni Kaukovuori, Student Member, IEEE, Jussi Ryynänen, Member, IEEE, and Kari A. I. Halonen, Member, IEEE, “Multitone Fast Frequency-Hopping Synthesizer for UWB Radio, “IEEE TRANSACTIONS ON
MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 8, AUGUST 2007.
[44] Yingmei, Chen; Zhigong, Wang; Li, Zhang, “A 5GHz 0.18-μm CMOS technology PLL with a symmetry PFD, “ IEEE. ICMMT2008 Proceedings.
[45] Ching-Lung Ti, Yao-Hong Liu and Tsung-Hsien Lin, “A 2.4-GHz Fractional-N PLL with a PFD/CP Linearization and an Improved CP Circuit, “ IEEE, ISCAS 2008.
[46] Zhinian Shu, Ka Lok Lee, and Bosco H. Leung, Senior Member, IEEE, “A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer with a Fractional Divider
Dual-PLL Architecture, “ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO.
3, MARCH 2004.
[47] Adrian Maxim, “A 2-5GHz Low Jitter 0.13p.m CMOS PLL Using a Dynamic Current Matching Charge-pump and a Noise Attenuating Loop-Filter, “ IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE.