Chapter 3 Phase Lock Loop Theory and System Simulation
4.1 Quadrature voltage-controlled Oscillator
4.1.1 Operational Principle
In general, it has better phase noise performance by using LC tank voltage control oscillator in single chip integrated circuits. However, it must to employ passive component, spiral inductors which would consume a lot of chip area. It is also difficult to model the behavior of passive inductors exactly by simulation tools, so the taped out measurement results may have huge differences between simulations and the actual performance.
Nowadays, the ring oscillators have acceptable performance in phase noise behavior, and the spiral inductors would not be the necessary in the ring oscillator architecture. It could successfully save the space in the chip area and have wider frequency tuning range. Moreover, it is highly integrated in mixed signal ICs. Because of these advantages, it is popularly used in the early microprocessor clock generator of low frequency spectrum. By the chip process goes progress, the ring oscillator start to be utilized in constant angular velocity phase lock loop of the high frequency clock generation, giga-bit microprocessor, and DVD/CD-ROM, etc……..
The architecture of ring oscillator is like fig 4.2 below. The inverters in ring oscillators could be (a) single-ended or (b) differential output. It becomes the ring structure by connecting the output of the last stage to the input of the first stage in multi-inverters. In integrated circuits, the differential pair is much more used because of its differential signal output.
(a) (b)
Figure 4.2 The architecture of the (a) single ended (b) differential output ring oscillators.
By Barkhousen Criterion, the oscillator is a positive feedback that the closed loop gain equals 1 and the phase shift of the loop is 2nπ, (n could be any integer). If we consider an odd number of the stages inverter based ring oscillator, every stage provides basic 180° phase shift.
And the phase shift caused by the output load R and the inner/outer parasitic capacitor C also should be thought over to achieve the left phase shift. For example, the 3-stage inverter basically provide phase shift as 3×180°=540°. We want to obtain the 2nπ=720° most nearest 540°, so each stage should supply extra phase shift,
(
720°−540°)
3=60°. The RC delay time is shown as t , and the delay of n stages is d2
Ntd =T ( T is the cycle time of the
loop). Therefore, the oscillation frequency is 1 2Ntd .
If we use the even number of the stages ring oscillator as the fig 4.3 below, the differential output of the last stage would be cross back to the input of the first stage. It forms a eight-stage inverter chain equaled 2n, and the inverter loop basically provides the phase shift as 180°×8=8π. In order to obtain the positive feedback to the phase shift 2nπ, the left phase shift would share the 2π degrees to the eight inverter stages. That means the delay time of each stage is t , and the d 2Ntd =T . Therefore the oscillation frequency is:
d
osc Nt
f 2
= 1 .
(4-1)
Figure 4.3 The architecture of the even number stages ring oscillator with RC equivalent delay.
The inverter gain and the phase shift of each inverter stage would be considered in the next step. We simply assume by first order approximate that each inverter stage contains a dominant pole formed by the load R and parasitic C. The transfer function of each inverter stage would be: The whole loop transfer function of the 3-stage inverter chain ring oscillator would be:
( )
3 3 The 3-stage inverter should support 180° for the loop to attain the 2nπ=720°, so each stage should provide the phase shift, 60°. In Bode plot, the equation of the frequency response in phase is as:
°
=
− 60
tan 1
o osc
ω ω
(4-4) Therefore, the ωosc = 3ωo, and ωosc substitute into the equation 4-2. The loop gain should be greater than 1, so the smallest gain of each inverter stage would be Ao ≥2.
By the same analysis, each inverter stage of the 4-stage differential ring oscillator would share the phase shift 45° (from 360° divide by 8), and the smallest gain of them would be
≥ 2 Ao .
I Stage
Q Stage V
controlBUFF
BUFF
Figure 4.4 The conceptual block diagram of the proposed two-stage ring oscillator.
Equation (4-1) shows that the increase of the oscillators speed can be realized by two ways: through the reduction of the delay time in the cell or by decreasing the number of cells in the ring oscillator. To decrease the delay time is limited by the process congenital
conditions. That cannot improve the oscillation speed too much. The reduction of the number of cells is very attractive not only for the operation speed increment but for the power
consumption reduction and the saving in area for its implementation. However, as N diminishes it is more difficult to satisfy the Barkhausen’s oscillation criteria that would be
discussed later. That is why we choose the two-stage ring oscillator, a challenge and a opportunity.
The conceptual block diagram of the proposed two-stage ring oscillator is shown in fig 4.4 above. It contains two differential inverter stages and the same control voltage. The output signal has in phase (I channel) and Quadrature phase (Q channel), two differential orthogonal frequency sources. The differential output of the Q stage would be cross back to the input of the I stage. It forms a four-stage inverter chain equaled 2n, and the inverter loop basically provides the phase shift as 180°×4=4π . In order to obtain the positive feedback to the phase shift 2nπ, the left phase shift would share the 2π degrees to the four inverter stages.
That means the delay time of each stage is t , and the d 2Ntd =T . Therefore the oscillation frequency is 1 2Ntd . The whole loop transfer function of the 4-stage inverter chain ring oscillator would be: As the analysis of the other stages ring oscillator, each stage of the two-stage ring oscillator should provide the phase shift, 90°. As a result of the impossibility of achieving 90° phase shift by unit RC stage, the traditional ring oscillator should have three inverter stages at least.
In order to attain the goal of two-stage ring oscillator, some circuit improvement would be presented in the next section.
The advantages of the two-stage ring oscillator are as follows:
1. It consumes less power dissipation (almost 21 power consumption of the four-stage ring oscillator).
2. It could oscillate at higher frequency (almost twice the oscillation frequency of the four-stage ring oscillator).
3. It occupies less chip area (almost 21 chip area of the four-stage ones).
4. two-stage ring oscillator generates the quadrature phase sine-wave signal with the minimum components.
4.1.2 Design Consideration [21], [25], [26], [27], [28]
For a two-stage ring oscillator, the demands for high speed, low power consumption and quadrature outputs, dictate oscillators of single two stages. However, a simple differential structure in the delay cell fails satisfying the oscillation conditions, just as it is observed in fig 4.5 below. In this figure it is possible to identify a dominant pole around 500MHz created by the time constant in an output node of the cell and a zero at very high frequency (100GHz), above which the magnitude of the gain ends up being flat. The zero comes from the gate-drain capacitance of the transistor M1 in the differential pair and it causes that the absolute phase shifts from 90º to 180º. If this cell was used in a two-stage ring oscillator, the system would not oscillate because the gain is under 0dB at the frequency in which the absolute phase changes 90º, causing the insufficient gain problem.
(a) (b)
Figure 4.5 The differential delay cell: (a) circuit diagram, (b) frequency response.
It is possible to generate the oscillation if one adds a mechanism that can provide a bigger change in the phase of the delay cell. An approach is to increase the dc gain and the shift phase of the cell simultaneously using differential amplifiers in parallel [22].
Nevertheless, even when the speed is increased the power consumption stays high, due to the use of four delay cells. In the delay cell of the proposed VCO shown in fig 4.6 below, extra circuitry is not required, the wanted characteristics are obtained by means of positive partial feedback [23] generated by M1a and M2a. The transistors M3 and M4 or M5 and M6, form a voltage controlled symmetrical load [24] that substitutes the resistor R of the fig 4.5 such that the delay time of the cell can be modified when the control voltage is changed (Vcon') along with the VCO oscillation frequency. The use of this load type allows diminishing the
sensibility to variations in common mode and the noise of phase of the circuit [24]. As shows fig 4.6, the partial positive feedback increases the gain of the cell, at the same time that it provides the necessary delay (the pole moves to the left) and the Barkhousen criteria are
simultaneously satisfied. That means when you design a differential inverter stage, you should verify that gain is above 0dB at the frequency in which the absolute phase changes 90º.
(a) (b)
Figure 4.6 The differential delay cell with partial positive feedback: (a) circuit diagram, (b) frequency response.
The transfer function of the proposed delay cell can be written in the following way:
⎟⎟
Therefore, the differential delay cell of the ring oscillator should satisfy the following conditions:
1. When the phase shift changes absolutely 90º in frequency response, the gain should be greater than 0dB.
2. Changes in one input phase must let the both two output phase change.
3. It needs the ability of high common mode rejection ratio (CMRR). The input of the delay cell will relate to the CMRR value. The higher transconductance of the input, the more assurance it will oscillate and the higher frequency. But that will consume more power.
4. Use the cross couple pair as latch to generate the positive feedback and let the output voltage difference larger.
5. The stronger the coupling of the latch, the more assurance it would oscillate. But the stronger the coupling of the latch, the lower oscillation frequency it would be.
Figure 4.7 The first version of the designed differential delay cell.
The first version of the designed differential cell is shown in fig 4.7 above. It contains a differential amplifier, M1, M3, M4, M6, and Mc. And the M2 and M5 form a cross couple
pair as a latch to provide the negative resistor cancelling the positive resistor. That could obtain the 90º phase shift. Due to the differential pair is completely symmetric, the Mc and Mb would be virtual ground. In order to analyze the circuit conveniently, we would assay it with half circuit as the following fig 4.8.
Vi+
Vout-Vout+
M1 M2
M3 M7
VB Vctrl
Figure 4.8 The half circuit of the designed differential delay cell.
And the corresponding small signal equivalent model of the differential delay cell half circuit is shown in fig 4.9 (a) below. The fig 4.9 (b) is the rearrangement of the small signal equivalent model.
(a)
Figure 4.9 The small signal equivalent model of (a) the half circuit (b) with rearrangement.
From the fig 4.9 (b), we could know the V to i V transfer function: o
In order to satisfy the Barkhausen’s criteria, the phase shift of each delay cell must achieve 90 degree and the gain must be greater than 1. When
L
m R
g 1
2 = , the real part of the transfer function would counteract and it become pure capacitance. That could let the phase shift come to 90º. When the
L
m R
g 1
2 = , the absolute value of the transfer function would be:
( )
Therefore the oscillation frequency is:L We could vary the output oscillation frequency by changing the gate voltage of the MOS M1.
That would change the g to vary the oscillation frequency. m1