Chapter 3 Phase Lock Loop Theory and System Simulation
4.2 Prescaler and Dividers
In this work, the programmable integer-N frequency divider is based on a simple divider chain. The division number of the PLL is 108 which are formed by two divide by 2 and three divider by 3. The divider chain is connected between the output of the ring oscillator and one of the phase frequency detector’s input. The design issues of the prescaler and the dividers are presented as follws:
4.2.1 Operational Principle
The prescaler and the dividers in this work are used the conventional structures which are widely utilized in nowadays IC design. The divided_by_2 circuits are based on a D flip-flop architecture shown in fig 4.18 below, which is superior at its wide input frequency range and can operate down to a very low frequency [29]. The divided_by_2 frequency dividers employ two D-latches in a master-slave configuration with negative feedback. One of the latches is positive clock cycle triggered, the other is negative one. In high speed master-slave dividers, it is common practice to design the slave as the “dual” of the master so that they could be both driven by a single clock. However, duality requires one of the latches to incorporate PMOS devices in the single path, hence lowering the maximum speed. To avoid the problem, the divider could be driven by two complementary clocks and the skew on each single path must be minimized [30].
D Q
D Q Q
Figure 4.18 The architecture of the D flip-flop based divide_by_2 frequency divider
The divide_by_3 frequency dividers are also based on two D flip-flops but the addition of an AND gate between the two D flip-flops. That could let the latches lock the clock cycle later half a period to achieve the goal of divide_by_3. Besides this, the other operational principles are the same as the divide_by_2 frequency dividers. The architecture of the divide_by_3 circuit is show in fig 4.19 below.
Q
Q Q
Figure 4.19 The architecture of the D flip-flop based divide_by_3 frequency divider
4.2.1 Design Consideration [32], [39]
The divider is designed to self-oscillate, that is if the input amplitude is set to zero, the output will still oscillate at some frequency. This is a desirable characteristic that the divider operates correctly with low input amplitude at its input frequency near 2 times the self-oscillating frequency. Furthermore, the required minimum amplitude for input signal increases as its frequency deviates from self-oscillating frequency which limits its operating range of the divider. For the input signal given at some frequency without sufficient amplitude, it would cause the divider malfunction. Therefore, output signal frequency would not be the half of the input signal frequency. While the minimum tolerable input amplitude is associated with the input MOS size of the divider [31], the large size of it results the smaller input required amplitude, nonetheless, this also results in a extra loading capacitance of proceeding stage degrading the speed of self-oscillating frequency.
Due to the output frequency of the 2-stage ring oscillator is at a high frequency, 7128 MHz, the prescaler and the divide_by_2 divider would choose the dynamic current mode architecture that would increase the speed of the frequency division. The output of the oscillator is as the clock cycle of the D flip-flop in fig 4.18, therefore, the first cycle of the oscillator would change the output of the positive cycle triggered latch to import to the negative cycle trigger latch. And it must wait until the second cycle of the oscillator come, the output of the negative cycle triggered latch would change. Thus it could be seen that the oscillator changes two clock cycles, and the divide_by_2 changes only one. Therefore it achieves the ability of divide_by_2. The dynamic D flip-flop among the divide_by_2 frequency divider is as fig 4.20 below. The VB is the bias voltage of the latches.
D D
CLK CLKB
VB VB
Q Q D D
CLK CLKB
VB VB
Q Q
VDD
VDD VDD VDD
Figure 4.20 The circuit diagram of the dynamic D flip-flop for the divide_by_2 frequency dividers
Using the left positive cycle triggered latch as the example, when the clock cycle is positive, the differential pair would preliminarily separate the outputs, Q and Q according to the height of the D and D . While the negative clock cycle comes, the separated outputs,
Q and Q would be apart from each other further by the positive feedback cross couple pair.
The operating principle of negative clock triggered latch is almost the same as the positive one, but the difference between the positive or negative clock cycles.
Q
Figure 4.21 The static D flip-flop for the divide_by_3 frequency dividers
Owing to the output signal of the ring oscillator cross the two divide_by_2 frequency dividers would be lower frequency (7128÷2÷2=1782 MHz), the structure of the dynamic current mode latch would cost too much power consumption. The static logic D flip-flop based dividers could be adopted to save the power consumption. Fig 4.21 shown above is the
architecture of the D flip-flop for the divide_by_3 frequency dividers. It is made from transmission gates and inverters that the ratio of the PMOS and NMOS equals 2. The AND gate in fig 4.19 is used the conventional complementary structure. The followings is the simulation results of the prescaler and dividers.
4.2.3 Circuit Realization
Fig 4.22 (a) shows the simulation results of the prescaler with input frequency, 7128 MHz, and fig 4.22 (b) is the simulation result the next divide_by_2 frequency divider with 3564 MHz input signal. In the waveforms, the functions of the dividers work correctly. The average current consumption of the prescaler is 2.17 mA, thus the power consumption is 2.61 mW. The next divide_by_2 divider cost current 0.96 mA, and the power consumption is 1.15 mW. The minimum input amplitude of the both dividers could be smaller than 10 mV at the objective input frequency, 7128 MHz and 3564 MHz, and they could function correctly between the range that input frequency add or subtract 1 GHz under input amplitude 100mV.
7128 MHz input
3564 MHz output
(a)
(b)
Figure 4.22 The simulated waveforms of (a) prescaler, and (b) divide_by_2 frequency divider
Fig 4.23 (a) shows the simulation results of the first divide_by_3 frequency divider connected after the divide_by_2 frequency divider with input frequency, 1782 MHz, and fig 4.22 (b) is the simulated waveform of the second divide_by_3 frequency divider with 594 MHz input signal. Finally, the last divide_by_3 frequency divider is connected between the
second divide_by_3 and PFD with input frequency, 198MHz. In the waveforms, the functions of the dividers work correctly. The average current consumption of the 1st divider is 0.54 mA, thus the power consumption is 0.64 mW. The 2nd divide_by_3 divider cost current 0.15 mA, and the power consumption is 0.18 mW. The current consumption of the last divide_by_3 divider is 0.049 mA, and the power consumption is 0.059 mW. The minimum input amplitude of all the divide_by_3 frequency dividers could be smaller than 30 mV at the objective input frequency, 1782 MHz, 594 MHz, and 198 MHz. They could function correctly between the range that input frequency add or subtract 30% themselves under input amplitude 300mV.
1782 MHz input 594 MHz output
(a)
594 MHz input 198 MHz output
(b)
198 MHz input 66 MHz output
(c)
Figure 4.23 The simulated waveforms of (a) the first, (b) the second, and (c) the last divide_by_3 frequency dividers
Finally, we connect the two-stage voltage control ring oscillator and the divide_by_108 frequency divider. The total current consumption of the oscillator and dividers are 22.75 mA,
thus the power consumption of them are 27.30 mW. The simulated waveforms function correctly in the fig 4.24 below.
VCO output 7128 MHz Divide_by_108 66 MHz
Figure 4.24 The simulated waveforms of the ring oscillator and the divide_by_108