Chapter 2 A 3.1~10.6 GHz CMOS Frequency Synthesizer
2.5 Discussion and Comparison
As we mentioned in chapter 2 section 2, the better frequency planning we used, the less circuit components and system disadvantages are revealed. In the followings, the frequency planning architecture for MB-OFDM UWB applications would be compared with previous works at system level. Each frequency planning architecture has its own logical thinking to improve some of the frequency synthesizer’s performance. However, in order to reach the goal covering the 7.5 GHz frequency spectrum and satisfying the UWB specifications, there must be some cost. How to let the cost down and achieve the same purpose is the great issue for us to pay efforts on it. Table 2.2 is the comparison of the proposed frequency planning architecture with the illustrated works in chapter 1.
Table 2.2 The summary and comparison of the UWB frequency synthesizer characteristics
This work [4]
The frequency planning architecture at system level of this work has superior advantages on low spurious response, uncomplicated system design, and saving much more chip area for UWB application. As compared to [4], the SSB of this work does not need to operate in very wide bandwidth (over 5 GHz frequency spectrum), and dividers in [4] is also a difficulty to realize. The architecture of [5] must waste an extra SSB mixer to realize the whole system.
That causes not only chip area consumption but the lower spurious response. [6] is realized for the past UWB frequency planning specification, and the chip area of [6] is huge because of its poly phase filters. The I/Q mismatch problem is another issue for [6] because the poly phase filter cannot operate exactly at wide frequency range. The SSB mixer in PLL also might cause extra problem in locking and spurious consideration in [6]. The [7] uses extra SSB mixer causing the issue as [5], but [7] only need one PLL. Although this work has more one PLL, we use two-stage ring oscillator to save the chip area. Without the passive component inductor, the chip area would even be smaller than [7]. Finally, in all the frequency generation schemes, this work is the most directly perceived through the sense, and the system is the most uncomplicated to realized.
Chapter 3
Phase Lock Loop Theory and System Simulation
Among the circuit component of frequency synthesizer, the phase-lock-loop is the major part of it. Synthesizers used in commercial radio receivers are largely based on
phase-lock-loops ( PLLs). Transceivers’ LO signals are generally produced by it. Because of this, the PLLs play an important role in the radio communications.
Phase-lock-loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a "reference" signal. A phase-lock-loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-lock-loop is an example of a control system using negative feedback. It is widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-lock-loop building block, the technique is widely used in
modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertz. The next section is the general consideration of the PLLs.
3.1 Basic Considerations
Phase Noise
A purity of spectrum synthesized output signal is the most important requirement in all
wireless communication systems. Ideally, the output spectrum of a frequency synthesizer should be a pure tone at the desired frequency, as shown in fig 3.1 (a) below. In the time domain, the output can be expressed as:
vout( )t = ⋅A cos(ω0t)
(3-1) However, due to random amplitude and phase fluctuations, the actual output becomes:
[ ] [ ]
( ) ( ) cos 0 ( )
out t
v = A+ε t ⋅ ω t+θ t
(3-2) Where ε( )t represents amplitude fluctuations and θ( )t represents phase fluctuations. The actual output spectrum exhibits “skirts” around the desired carrier impulse in the frequency domain, as shown in fig 3.1 (b) below. Because the amplitude fluctuations can be removed or greatly reduced by a limiter, the phase fluctuations, expressed in terms of phase noise, become a bigger and dominant concern in frequency synthesizer design. The phase fluctuations could be attributed to either the external noise at the frequency-tuning input of the oscillator or the noise sources such as thermal, shot, or flicker noise of the devices in the oscillator.
(a) (b)
Figure 3.1 The (a) ideal, (b) actual output spectrum of an oscillator
The phase noise limits the quality of the synthesized signal. In order to quantify the phase noise, the total noise power within a unit bandwidth at an offset frequency (Δω) from the carrier frequency (ω0) is compared with the carrier power. As shown in fig 3.1 (b) above,
this quantity is defined as:
{ }
10 log sideband( 0 ,1 )carrier
P Hz
L P
ω ω
ω ⎡ + Δ ⎤
Δ = ⋅ ⎢ ⎥
⎣ ⎦ (dBc / Hz) (3-3) Where Psideband(ω0+ Δω,1Hz) represents the single sideband noise power within a 1Hz bandwidth at an offset frequency (Δω).
Fig 3.2 below illustrates the impact of the oscillator or synthesizer phase noise in both the receive path and transmit path of a transceiver. As depicted in fig 3.2 (a), in the receive path, the weak desired signal is accompanied by a larger interferer in the adjacent channel.
Ideally, the received RF signal is down-converted with a pure LO signal into the desired pure IF signal and the down-converted interferer can be easily filtered. However, in fact, there exists a phase noise skirt around the LO signal. After down-conversion, the weak desired signal could be corrupted by the tail of the interferer spectra and even possibly canceled if the phase noise skirt is too large. It degrades the SNR of the desired signal. In the transmit path, the weak nearby signal of interest can be corrupted by the tail of the large-power transmitted signal, as shown in fig 3.2 (b).
(a) (b)
Figure 3.2 The effect of phase noise in (a) the receive path, (b) the transmit path
Therefore, the output spectrum of the LO or synthesizer must be extremely sharp, and a set of stringent phase noise requirements must be achieved so as to satisfy the maximum blocking signal power specified in the wireless communication system.
Settling Time
Transient behavior of the frequency synthesizers is also a critical performance parameter.
A change in the division ratio of divider or in the reference frequency would result in a loop transient. Every time a different division ratio or reference frequency is set for channel selection, the synthesizer requires a finite time to lock to the new frequency. The synthesizer needs settling to certain accuracy within the specification of the wireless standard and the overall required time is called “settling time” (also called “locking time”). Also, one thing worth mentioning is that the locking speed requirement of synthesizers is even more stringent for a fast frequency-hopping spread-spectrum system. However, in the UWB specifications, the switching time to the other frequency bands is only 9.47 ns, it is impossible for PLL to lock in such a tiny time. Therefore, changing the frequency bands by settling time of one PLL is not a solution for UWB application. The detailed analysis to model the loop settling behavior will also be discussed in later sections.
Tuning Range
The basic requirement set for a frequency synthesizer by any wireless communication system is that the synthesizer must be able to generate all required frequencies of the system with a sufficient accuracy for channel selection. Therefore, the voltage-controlled oscillator (VCO) and the prescaler must be carefully designed so as to cover the required dynamic frequency range of the synthesizer. However, in our frequency planning architecture, the output frequency of the PLLs should be fixed and unique. This is because of the settling time
of PLL cannot satisfy the UWB specifications (9.47ns).
Spurious Response
Apart from the phase noise, the other key parameter affecting the purity of spectrum synthesized output signal is the relatively high-energy spurious tones (also called spurs), appearing as spikes above the noise skirt, as shown in fig 3.3 (a) below.
Figure 3.3 The (a) spurs, (b) effect of spurs in receive path
Any systematic disturbance on the tuning input of the oscillator will cause the periodic phase variation and thus modulate the synthesized output. In the frequency domain, it manifests itself as the undesired tones at the upper and lower sideband of the carrier. These tones can be quantified by the difference between the carrier power and the spurious power at certain frequency offset in the dBc unit. As illustrated in fig 3.3 (b), similar to the case of phase noise, if a large interferer is close to the weak desired signal and the LO signal has spurs, then both the desired signal and interferer will be mixed down to the IF. If the spacing between the desired signal and the interferer is equal to that between the LO signal and the spur, the spur in the down-converted interferer falls into the center frequency of the desired down-converted signal, and then also degrades the SNR performance. The most common type
of spur is the reference spur that appears at multiples of the comparison frequency. Due to the non-ideal switching nature of the synthesizer, it may cause reference frequency feed-through, and then the resulting periodic ripples on the tuning input of the oscillator induces the reference spurs at the output, as shown in fig 3.4 below.
Figure 3.4 The feed-through of the reference frequency
The basic considerations would be analyzed and considered in the later section, and it also be the most important issues in the PLL design specifications. The performance of the frequency synthesizer is compared with them. How to achieve the specifications the frequency synthesizer needed is a tough task.
3.2 Phase-Lock-Loop Architecture
Phase-lock-loop based frequency synthesizer is the most popular in the communications systems. With the ability of high-integration in low-cost CMOS process, the PLL based frequency synthesizer is incomparable and unique. In order to achieve the frequency planning algorithm we designed, we should choose the most satisfying PLL architecture fit in with the UWB specification requirement from numerous PLL types. The integer-N is the most suitable PLL architecture for the demand we need.
3.2.1 Integer-N Architecture
The generic PLL-based frequency synthesizer generates its output by phase- locking the divided output to a reference signal. Due to low cost IC solutions, a charge pump is widely used in PLL-based frequency synthesizers nowadays. As shown in fig 3.5 below, an ideal charge pump combined with an ideal phase-frequency detector (PFD) provides an infinite dc gain with passive loop filters, which results in an unbounded pull-in range and zero static phase error. “Integer-N” means that the division ratio N of the frequency divider is a variable integer. In other words, the synthesized output frequency is integer multiples of the input reference frequency. In general,f is fixed and the frequency step or channel spacing is ref
equal to f . Various frequencies are achieved by changing the division ratio N. In the locked ref state, the output frequency is as follows:
out ref
f = ⋅N f
(3-4)
Figure 3.5 A simple charge pump PLL as frequency synthesizer
In the design of integer-N frequency synthesizers, to achieve the well frequency resolution, a low f is needed. This low ref f yields a high division ratio as well as a ref
narrow loop bandwidth. However, a narrow loop bandwidth results in slower settling speed of transients and deteriorates the in-band phase noise. So, the loop performance of the integer-N architecture is intrinsically limited by the standard-specified frequency resolution. Generally, a larger loop bandwidth is desired to achieve a faster dynamic loop response and suppress the VCO close-in phase noise, but otherwise the reference frequency leakage becomes serious.
Additionally, as a rule of thumb, the loop bandwidth should be ten times less than f for ref the consideration of the loop stability under linear, continuous-time approximation [16].
Although the trade-off of the reference frequency between the loop bandwidth and the frequency resolution, the frequency resolution issue is not considered in our PLL. The phase-lock-loop in UWB frequency synthesizer would not change its frequency as we mentioned in previous chapter. The frequency synthesizer needs fixed frequencies to generate the frequency scheme. Therefore, the integer-N architecture PLL is more convenient and easy to realize for the requirement we want.
3.2.2 System Specifications
Due to satisfy the specifications for MB-OFDM UWB application, the PLL should conform to the demands of frequency synthesizer architecture. The frequency planning algorithm in chapter 2 needs the fundamental PLL as frequency generation as 7128 MHz. In the followings, the expected specification for the PLL would be presented. The proposed PLL architecture is as follows (fig 3.6). The reference frequency in this work is produced from signal generator outside the chip. Considering the integration for future work, the reference frequency 66 MHz is decided by the crystal oscillator which can popularly and simply generate. Division number can be decided as the output frequency and the reference
frequency appearing. The lock time in proposed architecture is not an issue, so it is chosen as 50μs. Phase noise is -10 dBc/Hz less than the whole architecture we design in chapter 2 as the margin. Considering to save the chip area or convenient to make off chip, the loop filter would be chose as second order structure. It would be discussed in the later section. This work would be realized with TSMC 0.13μm process.
Figure 3.6 The proposed PLL architecture
Table 3.1 is the expected specification for the proposed PLL in order to satisfy the specified UWB frequency synthesizer architecture.
Table 3.1 The specification for proposed PLL
parameter value
Output frequency f out 7128 MHz Reference frequency fref 66 MHz
Loop filter order 2nd Division number N 108 Lock time t s 50μs Supply voltage VDD 1.2 V Phase noise @ 1MHz < -96.5 dBc/Hz
Process TSMC 0.13μm
3.2.3 Phase Noise Analysis [17], [18]
From the arrangement in the previous section, we set up the phase noise specification for frequency synthesizer in our application. In this section we would analyze the whole phase noise in PLL further in order to fit in with the specification for the proposed frequency generation scheme. The PLL-based frequency synthesizer suffers from noise introduced at the input or generated by the other components, such as PFD, CP, VCO, loop filter, and frequency divider, etc. It is important to get insight into how these noise sources affect the overall noise performance of synthesized output signal. These noise sources may be classified into two main types to sum up: one is the noise of VCO and the other is the noise from other sources.
The effect caused by each of these noise sources can be seen from the closed-loop transfer functions.
Figure 3.7 Noise sources of type II 3rd PLL linear model
Fig 3.7 illustrates an analytic linear model of the type-II third-order PLL with noise sources added. Based on this linear model, the transfer function from each noise source to the output can be derived so that we can quantify how much each noise source contributes to the output signal. These noise sources can be characterized as follows:
θnPFD: the noise arises from timing jitter caused by additive noise, predominantly thermal noise within PFD.
θnCP: the noise comes from thermal and flicker noise of each transistors in each current
source. (i.e. In2 4 m f KT gγ
∝ =
Δ )
θnLF: the mainly equivalent thermal noise of resister RP inside the loop filter. (i.e.
4KTRP
∝ )
θnVCO and θnref: the noise sources from VCO and the crystal reference oscillator, respectively.
θnBAK: the noise sources from the feedback path such as prescaler and dividers respectively.
The transfer functions for these noise sources can be derived as )
) We have already deliberated the transfer function for every noise sources above. The overall output phase noise θnout(s) transfer function from each noise source can be expressed as
⎥⎥ that the noise contribution mainly comes from the reference oscillator, the frequency divider of feedback path, phase frequency detector, and charge pump. At high frequency (i.e. F(s) ≈ 1,
∞
→
s ), θnout(s)≈θnVCO, which reveals that the main noise contribution comes from the VCO phase noise.
Finally, the total quantity Φ(s)O of output phase noise θnout contributed by each noise source can be expressed as:
BAK of phase noise in output by each noise source respectively. The Φ(s) means the
corresponding noise sources frequency power spectrum. We could quantize and analyze every noise sources, and compute it with Matlab (in the next section) to get the contributions of each noise source. By means of it, the best loop bandwidth could be designed to gain the best performance of phase noise.
3.3 PLL System Simulation
The phase lock loop (PLL) system includes reference signal generator, phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage control oscillator (VCO), and divider. Each circuit block has its own system specification for the PLL system to integrate.
The purpose for the system simulation is to establish the loop to understand signal behavior in the transient state and the stable state. It could also have the idea about the influence caused by each circuit block. Furthermore, the specifications for every circuit block would be decided by the process of the system simulation. This should be a great ministration to design the integrated circuits. The auxiliary software for system in this section is Simulink of Matlab.
3.3.1 Design Consideration
The PLL system considerations are as fig 3.8 below:
Figure 3.8 System considerations for each block of PLL
The input frequency (reference frequency) is 66 MHz, and the output frequency is 7128 MHz. The division of the divider is 108. They are determined in the previous section. Besides them, all the other situation we should know for each blocks are the charge (discharge) currents in the charge pump, the LF order decision, the passive component value in LF, the VCO gain, and the phase noise model for VCO. There is also a very important property for the whole PLL system, the reliability consideration. It includes the phase margin and loop bandwidth analysis. The system simulation can also check the PFD working state by the Simulink, however it is easy to simulate the PFD circuit behavior in circuit level. The PFD would not model in system level.
The PLL system design would be start at the rough design of VCO circuit block. It could be done because we already have the output frequency quantity. The VCO gain so called
KVCO could be decided roughly. The second step is to establish the phase noise model of the VCO. It could design how much charge pump current we should choose for the requirement and waste least power consumption. The next procedure is to design the bandwidth of the whole PLL. Because the settling time of the PLL is not the most important characteristic for our synthesizer architecture, the loop bandwidth of PLL could be chose one of tenth of input
frequency. The passive component of loop filter would be design when we set up the reliability issue as phase margin 60°. All the important specifications could be decided to simulation the transistor level like this.
3.3.2 System Simulation
The system simulation procedure mainly divides into four parts: 1. the design of the KVCO, 2. the decision of the charge pump current, 3. the design of the loop bandwidth, and 4.
The system simulation procedure mainly divides into four parts: 1. the design of the KVCO, 2. the decision of the charge pump current, 3. the design of the loop bandwidth, and 4.