Circuit Implementation

The whole complete circuit to realize the new proposed sub-1-V curvature-compensated CMOS bandgap voltage reference is shown in Fig. 2.14. The new proposed sub-1-V curvature-compensated bandgap voltage reference is composed by two sub-1-V bandgap cores [55] with two operational amplifiers, which are designed with the two-stage structure. The startup circuit for the self-bias circuit is used to avoid the circuit working in the zero-current state, which is realized by MSN1∼MSN3 (MSP1∼MSP3) for bandgap reference with NPN (PNP) BJTs. The MSN1~MSN2 and MSP1~MSP2 form the functions of inverter in the startup circuits. The device dimensions (W/L) of MSN1 and MSP2 are chosen to be much less than one, respectively. To ensure a complete cutoff operation of MSN3 and MSP3, the device dimensions (W/L) of MSN3 and MSP3 should be designed with the considerations of both maximum supply voltage and operating temperature [55]. The low-voltage operational amplifiers also need the startup circuit to avoid the zero-current state. The same startup circuits in Fig. 2.14 also use in the low-voltage operational amplifiers with two-stage structure. The current IREF1 in Fig. 2.14 is produced by a sub-1-V bandgap voltage reference with PNP BJTs and a p-channel input pair of operational amplifier. The IREF1 can be expressed as

_

where R1_PNP is set to R1a_PNP + R1b_PNP (or R2a_PNP + R2b_PNP), R1a_PNP = R2a_PNP, and R1b_PNP = R2b_PNP. The current IREF2 is produced by another sub-1-V bandgap voltage reference with NPN BJTs and an n-channel input pair of operational amplifier.

Similarly, IREF2 can be expressed as R1b_NPN = R2b_NPN. Through the current mirrors, the difference current, IREF, between the IREF1 and IREF2 can be written as become a temperature-independence current. Therefore, a temperature-independence voltage can be achieved across RREF, which has the lower temperature coefficient. The output reference voltage can be expressed as

2 2 1 1

Thus, the new proposed sub-1-V bandgap voltage reference with new curvature-compensated technique has the excellent curvature-compensated result.

The minimum supply voltage of the new proposed sub-1-V curvature-compensated bandgap voltage reference can be expressed by

1 _

where VTHP and VTHN are threshold voltages of the PMOS and NMOS transistors, respectively. Since the base-emitter voltages (VBE_NPN and VBE_PNP) of the bipolar transistors in equation (2.16) are multiplied by the resistance subdivision, this circuit can be operated with sub-1-V supply voltage.

Because the operational amplifier of the bandgap voltage reference is not ideal, the offset voltage (VOS) of operational amplifier will increase error on output reference voltage of bandgap voltage reference. The bnadgap voltage reference in CMOS technology suffers from the effect of MOS transistor due to the mismatch of transistor dimensions and threshold voltage. In new proposed sub-1-V curvature-compensated CMOS bandgap voltage reference, the relationship between output reference voltage and offset voltage (VOS) of the operational amplifier can be rewritten by

2 2 1 1

where VOSN and VOSP are the offset voltage of the operational amplifiers with n-channel and p-channel input pairs, respectively. The effect of the VOSN and VOSP is amplified by the resistance ratio of K2R1_NPN / R1b_NPN and K1R1_PNP / R1b_PNP, respectively. However, this can be reduced by increasing the emitter areas ratio of the BJTs (NNPN and NPNP), and the required resistance ratio of K2R1_NPN / R1b_NPN and K1R1_PNP / R1b_PNP is reduced to minimize the negative impact from VOS [72]. In operational amplifier, the systematic offset can be minimized by adjusting transistor dimensions and bias current in ratio, while the random offset can be reduced by symmetrical and compact layout.

2.2.4. Simulation and Experimental Results 2.2.4.1. Simulation Results

The bandgap voltage reference with new proposed curvature-compensated technique has been simulated during the operating temperature from 0 to 100 °C. The temperature coefficient of the bandgap voltage reference with new curvature-compensated technique is around 7.5 ppm/°C under the supply voltage of 1 V. The dependence of IREF (output reference current) on the operating temperature from 0 to 100 °C is shown in Fig. 2.15 under the supply voltage of 1 V.

2.2.4.2. Silicon Measurement

The new proposed sub-1-V curvature-compensated bandgap voltage reference has been fabricated in a 0.25-μm CMOS technology. The proposed sub-1-V curvature-compensated bandgap voltage reference consists of the bandgap cores, bipolar transistors, and resistors. Fig. 2.16 shows the overall die photo of the new proposed sub-1-V curvature-compensated bandgap voltage reference. The occupied silicon area of the new proposed curvature-compensated bandgap voltage reference is only 480 μm × 226 μm. The active devices (MOSFETs) have been drawn in a common centroid layout to reduce process mismatch effect. The bipolar transistors in this chip are the parasitic vertical PNP BJTs and NPN BJTs. The ratio between the emitter areas of Q1_PNP and Q2_PNP (Q1_NPN and Q2_NPN) is 8. The total emitter area of Q1_PNP (Q1_NPN) is 200 μm² and that of Q2_PNP (Q2_NPN) is 25 μm² in the layout. The resistors in this chip are formed by un-salicided P+ ploy resistances, which have minimum process variation and temperature coefficient in the given foundry’s CMOS process, to improve the accuracy of resistance ratio. The bandgap voltage reference has been measured with the operating temperature varying from 0 to 100 °C. The power supply voltage was set from 0.85 to 1.2 V. The measured results are shown in Fig. 2.17. The measured data is measured by Agilent 4156. The temperature coefficient is around 13.4 ppm/°C with the supply voltage at 1 V. The experimental results in Fig. 2.18 have confirmed that the minimum supply voltage for the new proposed sub-1-V curvature-compensated bandgap voltage reference is 0.9 V with

temperature coefficient of 19.5 ppm/°C.

About the measurement setup for power supply rejection ratio (PSRR), a signal with sinusoidal ripple is added on power supply to measure the small-signal gain between the supply voltage and output reference voltage. The AC input signal at the power supply pin must include a DC offset of the normal power supply voltage, so that the bandgap voltage reference circuit remains powered up [67]. The averaged measured power supply rejection ratio (PSRR) is - 25.5 dB at 10 kHz, whereas the reference output voltage is 536 mV at 25 °C under the supply voltage of 0.9 V. The comparison among the proposed sub-1-V curvature-compensation bandgap voltage reference of this work with other prior-art curvature- compensation bandgap voltage references is summarized in Table 2.2. From this table, the exponential temperature compensation [69] and piecewise-linear curvature correction [62], [70] are realized by BiCMOS and BJT processes, respectively. The resistor temperature compensation [72]

in CMOS process requires a higher supply voltage to realize it. Those prior arts [62], [69], [70], [72] shown with very low temperature coefficients were achieved by trimming after silicon fabrication. In this work, the new proposed sub-1-V curvature-compensated bandgap voltage reference can achieve a low enough temperature coefficient without trimming in the general CMOS technology.

2.2.5.Summary

A new proposed sub-1-V curvature-compensated bandgap voltage reference with VREF of 536 mV and temperature coefficient of 19.5 ppm/°C under supply voltage of 0.9 V was presented, which consumes a maximum current of 50 μA at 0.9 V. The sub-1-V operation of the curvature-compensated bandgap voltage reference has been successfully verified in silicon. The new proposed curvature-compensated technique used to improve the temperature coefficient of sub-1-V bandgap voltage reference can be implemented in general CMOS technology. In order to improve the impact of process variation on performances of new proposed sub-1-V curvature-compensated bandgap voltage reference, the resistor with trimming network should be added into the proposed bandgap reference circuit.