Traditional Bandgap Reference Circuit

A typical implementation of bandgap reference in CMOS technology is shown in Fig. 2.1. In this circuit, the output is the sum of a base-emitter voltage (VEB) of BJT and the voltage drop across the upper resistor. The BJTs (Q1 and Q2) are typically implemented by the diode-connected vertical PNP bipolar junction transistors. The output voltage of the traditional bandgap reference circuit can be written as

2 1 second item in (2.1) is proportional to the absolute temperature (PTAT), which is used to compensate the negative temperature coefficient of VEB. Usually, the VPTAT voltage comes from the thermal voltage VT with a temperature coefficient about + 0.085 mV/°C, which is quite smaller than that of VEB. After multiplying VPTAT with an appropriate factor and summing with VEB, the bandgap reference will have a very low sensitivity to temperature. Hence, if a proper ratio of resistors is kept, an output voltage with very low sensitivity to temperature can be obtained. In general, the VREF

is about 1.25 V in CMOS process, so that the traditional bandgap reference circuit can not be operated in low voltage application, such as 1 V or below.

2.1.3. New Proposed Bandgap Reference Circuit

The design concept of the new proposed bandgap reference is that the two voltages (which are proportional to VEB and VT, respectively) are generated from the same feedback loop. The two-stage operational amplifier with p-channel input is used in this new proposed bandgap reference. The p-channel input has a lower input common-mode voltage than that of the n-channel input to keep the transistors working in the saturation region.

The new proposed bandgap reference is shown in Fig. 2.2, which uses the resistive subdivision R1a, R1b,R2a, and R2b to reduce the input common-mode voltage of the amplifier. The voltages V1 and V2 in Fig. 2.2 have a negative temperature

coefficient as that of VEB. In the traditional bandgap reference, the negative input of the operational amplifier is connected to VEB2, whose value is varying from 0.65 V to 0.45 V when the temperature is changed from 0 °C to 100 °C. The minimum supply voltage (VDD) of the traditional bandgap reference circuit needs VEB2+2|VDSsat|+|VTHp|.

The VTHp is the threshold voltage of PMOS. The supply voltage of the traditional bandgap reference is more than 1 V. In Fig. 2.2, the dimensions of PMOS devices M1

and M2 are kept the same. The resistance of R1a and R2a is the same, and the resistance of R1b and R2b is also the same. Following the KCL at the nodes of V1 and V2 in Fig.

2.2, the node equation can be written as

2 reference voltage VREF can be expressed as

1 1

The item of VREF-TRAD in (2.4) is identical to the traditional reference voltage in (2.1).

In order to achieve sub-1-V operation, the ratio of R1b / (R1a+R1b) is used to scale down the reference voltage level. Therefore, the minimum supply voltage of the new proposed bandgap reference can be effectively reduced to only

( ) 2 2

DD Min THp DSsat

V =V +V + V . (2.5) The new proposed bandgap reference can be operated under sub-1-V supply voltage.

The whole complete circuit to realize the proposed sub-1-V bandgap reference is shown in Fig. 2.3. The circuit is composed of a bias circuit, a bandgap core, two

startup circuits, and a two-stage operational amplifier. The bandgap reference circuit has two stable points. To ensure that it ends up to the correct state, a startup circuit must be added. The startup circuit for the bias circuit is used to avoid the bias circuit working in the zero-current state, which is realized by MS1a∼MS3a in Fig. 2.3 [55].

Similarly, another startup circuit is used to ensure that the input voltage of the amplifier is not kept at zero in the initial state. The MS1a and MS2a form a function of inverter in the startup circuit. The device dimensions (W/L) of MS2a and MS2b are chosen to be much less than one. When the circuit operates in zero-current state, the gate voltages of MS1a and MS1b are pulled high and close to VDD. The drain voltages of MS2a and MS2b are pulled low to turn on the MS3a and MS3b, which inject current to the bandgap core circuitry (by MS3b) and the bias circuit (by MS3a). The drain voltages of MB3 and M4 are decreased, therefore the bandgap core circuitry and bias circuit start to operate. Once the drain voltage of MB4 and the gate voltages of M1, M2, MA1, and MA6 are decreased, the drain voltages of MS1a and MS1b are pulled high to cut off MS3a

and MS3b. The device dimensions (W/L) of MS2a and MS2b are critical since the loop of the bandgap reference could be destroyed, if MS3a or MS3b were not completely cut off after startup. To ensure a complete cutoff operation of MS3a and MS3b, the device dimensions (W/L) of MS3a and MS3b should be designed with the considerations of both maximum supply voltage and operating temperature [55]. The capacitors C1 and C2 are used to stabilize the circuit. The bulk and the source of the input pair transistors MA2 and MA3 in the amplifier should be connected together to avoid the body effect.

In real-world applications, the power supply voltage is never perfect. It consists of a DC level plus AC noise caused by transient currents from circuit operations.

Another important factor of the bandgap reference circuit operated in sub-1-V supply voltage is the power supply rejection ratio (PSRR) [65], which represents the resistance against the noise from the supply voltage in the unit of decibel (dB). The small-signal model of the proposed bandgap reference circuit with the operational amplifier of p-channel input is shown in Fig. 2.4, where only considers the noise from the supply voltage. The resistances of R and ^'₃ R in Fig. 2.4 are R^'₄ 3 + (R1a // R1b) and R4 + (R2a // R2b), respectively. The capacitor C is the parasitic drain-to-bulk junction capacitance of M2. Since the turn-on resistance of the PNP transistors is small, both Q1 and Q2 can be simplified as short-circuit path to the ground. The

amplifier is modeled with an output resistor Rout and two voltage-controlled current sources id and idd, which are driven by the differential input voltage vd and power supply voltage vdd, respectively. The power supply rejection ratio (PSRR) of this new proposed bandgap reference circuit, which is the ratio of the output reference voltage and the noise from the supply voltage, can be expressed as

( ) 2

From (2.6), the PSRR of the proposed bandgap reference will become worse at high frequency. It is apparent that the pole location can be shifted by changing the capacitance at VREF node. Moving the pole to the left in the s-plane will result in an improvement in high-frequency noise rejection. This can be achieved by inserting a capacitance Cp to ground at VREF node. Thus, the PSRR in (2.6) is modified to

A larger Cp provides better stability, but the startup time will become longer. The pre-regulated circuit [73] also used to improve the PSRR of the bandgap circuit.

However, minimum supply voltage is the tradeoff.

The operational amplifier in Fig. 2.3 under sub-1-V operation has a limited gain.

Thus, there will be a nonzero input-referred offset voltage VOS. Considering the offset voltage of VOS, the VREF in (2.4) including the offset voltage can be written as

1 1

The offset voltage, VOS, is a temperature dependent voltage. To reduce the impact of VOS on VREF, the ratio of R4 / R3 should be designed as small as possible. The resistor ratio can be fabricated by CMOS technology with a very good percent.

2.1.4. Simulation and Experimental Results 2.1.4.1. Simulation Results

The proposed bandgap reference circuit has been simulated by varying its operating temperature from 0 to 100 °C. The dependence of VREF (output reference voltage) on the operating temperature is shown in Fig. 2.5 under difference power supply voltage (from 0.8 to 1.1 V). The temperature coefficient is around 75 ppm/°C with the supply voltage of 0.85 V. With supply voltage of 0.8 V, the temperature coefficient grows sharply to be above 200 ppm/°C. The dependence of VREF on the supply voltage is shown in Fig. 2.6 under the temperatures of 0, 25, and 100 °C. The curves of output reference voltages under the temperatures of 0, 25, and 100 °C grow together while the supply voltage of the proposed bandgap reference is above 0.85 V.

This means that the minimum supply voltage for the new proposed bandgap reference can be as low as 0.85 V. The PSRR at low frequency of the proposed bandgap reference, which works in the low supply voltage of 0.85 V, is - 30.2 dB.

2.1.4.2. Silicon Verification

The proposed bandgap reference circuit has been fabricated in a 0.25-μm single-ploy-five-metal (1P5M) CMOS process. Fig. 2.7 shows the overall die photo of the new sub-1-V bandgap reference circuit. The occupied silicon area of the new proposed bandgap reference circuit is only 177 μm × 106 μm. The active devices (MOSFETs) have been drawn in a common centroid layout to reduce process mismatch effect. The bipolar transistors in this chip are the parasitic vertical PNP BJTs in CMOS process. The ratio between the emitter areas of Q1 and Q2 is 8. The total emitter area of Q1 is 200 μm² and that of Q2 is 25 μm² in the layout. The resistors in this chip are formed by salicided ploy resistors, which have minimum process variation to improve the accuracy of resistance ratio. The bandgap reference circuit has been measured by varying its operating temperature from -10 to 120 °C.

The power supply voltage was set from 0.8 to 1.2 V. The measured data is measured by Agilent 4156. The measured results are shown in Fig. 2.8. The measured

temperature coefficient of the new proposed bandgap reference circuit is around 58.1 ppm/°C under the supply voltage of 0.85 V. The dependence of output reference voltage on the VDD supply voltage under different temperatures is shown in Fig. 2.9.

The experimental results in Fig. 2.9 have confirmed that the minimum supply voltage for this sub-1-V bandgap reference is 0.85 V.

About the measurement setup for power supply rejection ratio (PSRR), a sinusoidal ripple is added on power supply to measure the small-signal gain between the supply voltage and output reference voltage. The AC input signal at the power supply pin must include a DC offset that corresponds to the normal power supply voltage so that the bandgap reference circuit remains powered up [67]. The dependence of measured PSRR on the frequency under different input sinusoidal amplitudes is shown in Fig. 2.10. The averaged power supply rejection ratio (PSRR) is - 33.8 dB at 10 kHz, whereas the reference output voltage is 238.2 mV at 25 °C under the VDD power supply of 0.85 V. The comparison among the proposed sub-1-V bandgap reference of this work with other prior-art low voltage bandgap references is summarized in Table 1. The new proposed bandgap reference has the advantages of low operating voltage and low temperature coefficient in the general standard CMOS technology without special low-threshold-voltage device.

2.1.5. Summary

A CMOS bandgap voltage reference with VREF of 238.2 mV and temperature coefficient of 58.1 ppm/°C, which consumes a maximum current of 28 μA at 0.85 V supply, has been presented. The sub-1-V operation of the bandgap reference has been successfully achieved in this work without using the low-threshold-voltage devices.

Moreover, other techniques to achieve sub-1-V operation have been described, such as low voltage startup circuit and the lower common-mode input range of the amplifier by using the resistive subdivision method. Without using low-threshold-voltage device, the proposed bandgap reference circuit can be implemented in general CMOS technology. In order to improve the impact of process variation on performances of new proposed sub-1-V bandgap voltage reference, the resistor with trimming network should be added into the proposed bandgap reference circuit.

2.2. Curvature-Compensation Technique for CMOS Bandgap Reference Circuit With Sub-1-VOperation

2.2.1. Background

Reference circuits are the basic building blocks in many applications from pure analog, mixed-mode, to memory circuits. The demand for low-voltage operation is especially apparent in the battery-operated mobile products, such as cellular phones, PDA, camera recorders, and laptops [54].

In CMOS technology, the parasitic vertical bipolar junction transistors (BJT) have been used in high-precision bandgap voltage references. The conventional CMOS bandgap references did not work with sub-1-V supply voltage. The reason, why the minimum supply voltage can not be lower than 1 V, is constrained by two factors. One is due to the bandgap voltage of silicon around 1.25 V [55], [57], which exceeds 1-V supply. The other is that the low-voltage design of the proportional to absolute temperature current generation loop is limited by the input common-mode voltage of the amplifier [55], [57]. These two limitations can be solved by using the resistive subdivision methods [55], [59], low-threshold voltage (or native) device [58]-[60], BiCMOS process [57], or DTMOST device [61]. However, the bandgap reference working with low supply voltage often has a higher temperature coefficient than that of traditional bandgap reference. This has resulted in the development of new temperature compensated techniques, such as quadratic temperature compensation [68], exponential temperature compensation [69], piecewise-linear curvature correction [62], [70], and resistor temperature compensation [71], [72]. To implement those advanced mathematical functions with high accuracy, the development of the low-voltage bandgap structure requires precision matching of current mirrors or a pre-regulated supply voltage. Cascode current mirror [62], [68]

and pre-regulated circuit [73] are good methods to solve this problem, but the minimum supply voltage is the tradeoff to use such methods.

In this work, a new sub-1-V curvature-compensated CMOS bandgap reference is proposed to be successfully operated with sub-1-V supply in a standard 0.25- m 　

CMOS process. The new proposed sub-1-V curvature-compensated bandgap voltage reference with a stable output voltage VREF of 536 mV and temperature coefficient of 19.5 ppm/°C under supply voltage of 0.9 V has been verified in the silicon chip [74].

2.2.2. Non-Linearity Term of Traditional Bandgap Reference Circuit

The typical implementation of traditional bandgap voltage reference in CMOS technology is shown in Fig. 2.1. In this circuit, the output reference voltage is the sum of a base-emitter voltage (VBE) of BJT and the voltage drop across the upper resistance (R2). The BJTs (Q1 and Q2) are typically implemented by the diode-connected vertical PNP bipolar junction transistors. The output reference voltage of the traditional bandgap voltage reference circuit can be written as

( )

where k is Boltzmann’s constant (1.38×10^-23 J/K), q is electronic charge (1.6×10^-19 C), and N is the emitter area ratio of BJTs. The second item in equation (2.9) is proportional to the absolute temperature (PTAT), which is used to compensate the negative temperature coefficient of VBE. Usually, the proportional to the absolute temperature voltage (VPTAT) comes from the thermal voltage (kT q ) with a / temperature coefficient about + 0.085 mV/°C which is quite smaller than that of VEB. After multiplying VPTAT with an appropriate factor and summing with VBE, the bandgap voltage reference will have a low sensitivity to temperature variation.

However, the relationship between VBE of BJT and temperature is a non-linear property. That can be expressed by [75]

[ ]

where VG is the bandgap voltage of silicon extrapolated at 0 K, T is the absolute temperature in degrees Kelvin (^oK), η is a temperature constant depending on technology, m is the order of the temperature dependence of the collector current, and T0 is the reference temperature. In equation (2), the term of Tln(T/T0) is the nonlinear temperature-dependence factor to VBE. When equation (2.10) is expanded by Taylor

series, it can be represented by [75]

2

0 1 2 ... ⁿ

BE n

V =a +a T a T+ + +a T , (2.11) where a₀, a₁, ..., and a are the corresponding coefficients. The relationship _n between nonlinear temperature-dependence VBE and linear temperature-dependence VPTAT on the output reference voltage of bnadgap reference is shown in Fig. 2.11. The first-order temperature compensation involves the cancellation of the T term by using the VPTAT, but the high-order temperature-dependence factor can not be compensated with VPTAT in the traditional bandgap voltage reference. Therefore, the traditional bandgap voltage reference working in low supply voltage has a higher temperature coefficient.

2.2.3. Sub-1-V Bandgap Reference Circuit With Curvature- Compensated Technique

2.2.3.1. Design Concept

The proposed bandgap voltage reference with new curvature- compensation technique is illustrated in Fig. 2.12. There are two types of bandgap voltage reference circuits in standard CMOS process. The first type uses the parasitic vertical PNP BJTs to realize the badgap voltage reference circuit, which has been widely used in many integrated circuits. The second type is realized with parasitic vertical NPN BJTs. The parasitic vertical NPN BJT in standard CMOS process is implemented with deep N-well structure. Thus, there is no extra cost to have NPN parasitic transistor. The cross-sectional view of parasitic vertical NPN BJT in CMOS process is shown in Fig.

2.13. The emitter, base, and collector of parasitic vertical NPN BJT are realized by the N+ diffusion, P-well, and deep N-well layers, respectively.

The new proposed curvature-compensation technique has two output reference currents, IREF1 and IREF2, which areformed by two bandgap voltage references. The current IREF1 comes from a bandgap voltage reference with PNP BJTs, whereas the IREF2 is produced by another bandgap voltage reference with NPN BJTs. The output reference currents act with concave-up shapes in the temperature range from 0 to 100

°C, which are designed with the same center temperature (T0) where the temperature coefficient of IREF1 and IREF2 is zero. Through the current mirrors, a temperature-independence current generated from the difference between IREF1 and IREF2 can be produced to compensate the high-order temperature-dependence factor of VBE.

In Fig. 2.12, an output reference voltage VREF with very low sensitivity to temperature can be obtained across the resistance RREF. Thus, the new proposed curvature-compensated bandgap voltage reference has the excellent curvature-compensated result with low-voltage operation.

2.2.3.2. Circuit Implementation

The whole complete circuit to realize the new proposed sub-1-V curvature-compensated CMOS bandgap voltage reference is shown in Fig. 2.14. The new proposed sub-1-V curvature-compensated bandgap voltage reference is composed by two sub-1-V bandgap cores [55] with two operational amplifiers, which are designed with the two-stage structure. The startup circuit for the self-bias circuit is used to avoid the circuit working in the zero-current state, which is realized by MSN1∼MSN3 (MSP1∼MSP3) for bandgap reference with NPN (PNP) BJTs. The MSN1~MSN2 and MSP1~MSP2 form the functions of inverter in the startup circuits. The device dimensions (W/L) of MSN1 and MSP2 are chosen to be much less than one, respectively. To ensure a complete cutoff operation of MSN3 and MSP3, the device dimensions (W/L) of MSN3 and MSP3 should be designed with the considerations of both maximum supply voltage and operating temperature [55]. The low-voltage operational amplifiers also need the startup circuit to avoid the zero-current state. The same startup circuits in Fig. 2.14 also use in the low-voltage operational amplifiers with two-stage structure. The current IREF1 in Fig. 2.14 is produced by a sub-1-V bandgap voltage reference with PNP BJTs and a p-channel input pair of operational amplifier. The IREF1 can be expressed as

_

where R1_PNP is set to R1a_PNP + R1b_PNP (or R2a_PNP + R2b_PNP), R1a_PNP = R2a_PNP, and R1b_PNP = R2b_PNP. The current IREF2 is produced by another sub-1-V bandgap voltage reference with NPN BJTs and an n-channel input pair of operational amplifier.

Similarly, IREF2 can be expressed as R1b_NPN = R2b_NPN. Through the current mirrors, the difference current, IREF, between the IREF1 and IREF2 can be written as become a temperature-independence current. Therefore, a temperature-independence voltage can be achieved across RREF, which has the lower temperature coefficient. The output reference voltage can be expressed as

2 2 1 1

Thus, the new proposed sub-1-V bandgap voltage reference with new curvature-compensated technique has the excellent curvature-compensated result.

The minimum supply voltage of the new proposed sub-1-V curvature-compensated bandgap voltage reference can be expressed by

1 _

where VTHP and VTHN are threshold voltages of the PMOS and NMOS transistors, respectively. Since the base-emitter voltages (VBE_NPN and VBE_PNP) of the bipolar transistors in equation (2.16) are multiplied by the resistance subdivision, this circuit can be operated with sub-1-V supply voltage.

Because the operational amplifier of the bandgap voltage reference is not ideal,

Because the operational amplifier of the bandgap voltage reference is not ideal,

在文檔中 低電壓互補式金氧半製程下的類比電路設計與可靠度 (頁 43-0)