Chapter 6. New Gate Bias Voltage Generating Technique With Threshold-Voltage
6.2. Impact of Threshold-Voltage Variation on TFT I-V Characteristics
In general, the TFT devices on glass substrate are usually designed in saturation region for analog circuit applications. The small-signal gain and frequency response of analog circuits in LTPS process are determined by transconductance (gm) and output resistance (ro) of TFT devices. The small-signal parameters of transconductance (gm) and output resistance (ro) in TFT devices can be expressed as, respectively, where μ is the mobility of carrier, L denotes the effective channel length, W is the effective channel width, Cox is the gate oxide capacitance per unit area, VTH is the threshold voltage of TFT device, VGS is the gate-to-source voltage of TFT device, VA
is the Early voltage, and ID is the drain current of TFT device. Comparing equations (6.1) and (6.2), the drain current ID is the major factor for analog circuits in LTPS process. Therefore, the performances of analog circuits in LTPS process are dominated by drain current of TFT device. The drain current ID of TFT device operated in saturation region can be expressed as
1 2
The channel-length modulation of TFT device is not included in equation (6.3). The threshold voltage (VTH) of TFT device is an important parameter in equation (6.3), so the threshold-voltage variation among TFT devices will cause the variation on drain currents of TFT devices to degrade the circuit performances in analog circuits on glass substrate. How to design a stable biasing circuit with threshold-voltage compensation to reduce non-uniformity of performances in analog circuits over the whole panel in LTPS process is an important design challenge.
The HSPICE with Monte Carlo Analysis can be used to simulate and analyze the impact of threshold-voltage variation on drain current of TFT device. The threshold-voltage variation of TFT device on glass substrate can be modeled by Gaussian distribution. The simulated waveforms of N-TFT drain current ID with 50
% threshold-voltage variation of Gaussian distribution under different gate voltages VG in a 8-μm LTPS process is shown in Fig. 6.1. The dimension of N-TFT device is 80μm/8μm. The gate voltage is biased from 1.3 V to 4.3 V. In order to confirm that N-TFT device is operated in saturation region, the drain voltage of N-TFT device is also biased from 1.3 V to 4.3 V to keep gate-to-drain voltage of zero volt. The simulated result shows that the N-TFT device with 50 % threshold-voltage variation of Gaussian distribution causes the drain current with a variation as large as 22 μA in LTPS process. Therefore, the large variations on drain currents of TFT devices will cause large mismatches on the biasing voltages and currents in analog circuits to further result in non-uniformity of performances in analog circuits over the whole panel. For the System-on-Plane (SoP) applications, to reduce the impact of threshold-voltage variation on performance among analog circuits in LTPS process is a very important design challenge.
6.3. New Proposed Gate Bias Voltage Generating Technique With Threshold-Voltage Compensation
6.3.1 Design Concept
The new proposed gate bias voltage generating technique with threshold-voltage compensation is illustrated in Fig. 6.2. The biasing current ID_MC is a small current used to bias the MC device operated in weak inversion region. When the MC device operated in weak inversion region, the gate control voltage VGC can be written as
_
GC BIAS TH MC
V ≅V +V , (6.4) where VTH_MC is the threshold-voltage of MC device, and VBIAS is the applied biasing voltage. The drain current ID_MD of MD device can be expressed as
2 drawn with the same device dimension. The threshold-voltage difference between MC
and MD devices can be reduced as small as possible by symmetrical and compact layout in an adjacent location. Therefore, the equation (6.5) can be further rewritten as
The drain current ID_MD of MD device can become independent on the threshold voltage and dominated by the VBIAS voltage. The new proposed gate bias voltage generating technique with threshold-voltage compensation does not need any extra clock signal and capacitor to reduce the impact of threshold-voltage variation on the biasing circuit for analog circuits in LTPS processes.
6.3.2.Circuit Implementation
The complete circuit of the proposed gate bias voltage generating technique with threshold-voltage compensation for analog circuit applications in LTPS technology is shown in Fig. 6.3. The new proposed gate bias voltage generating circuit with threshold-voltage compensation is formed with M1, M2, M3, M4, M5, and M6 devices.
The M1, M2, M5, and M6 devices form the current mirror. In order to reduce the power consumption and chip area of the new proposed gate bias voltage generating circuit, the M3 and M4 devices are used to realize the referenced current source. The M3 and M4 devices are operated in saturation region o generate a biasing current through the current mirror of M1, M2, M5, and M6 devices to bias MC device operated in weak inversion region. The voltage VC can be expressed as
_ 3 _ 4
( ) ( )
43 generating circuit. The biasing current ID_M4 and ID_MC can be written as, respectively,( )
2 especially designed much larger than one to reduce the impact of biasing current (ID_M4) variation on gate control voltage (VGC) of the new proposed gate bias voltage generating circuit.The simulated gate control voltage VGC of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages VBIAS is shown in Fig. 6.4. The typical threshold voltage of N-TFT device in 8-μm LTPS process is approximately 1.3 V. The VBIAS voltage is biased from 0 V to 3V. The gate control voltage VGC is changed from 1.3 V to 4.3 V. The gate control voltage VGC of the new proposed gate bias voltage generating circuit with threshold-voltage compensation is approximately VBIAS+VTH_MC. The HSPICE with Monte Carlo Analysis is used to verify the function of the new proposed gate bias voltage generating circuit with threshold-voltage compensation in LTPS technology.
The simulated gate control current VGC of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under the different biasing voltages VBIAS with the 50 % threshold voltage variation (Gaussian distribution) of N-TFT and P-TFT devices is shown in Fig. 6.5. The variation on gate control voltage VGC, which can be used to compensate the threshold-voltage variation of TFT device in LTPS process, is 0.675 V. The simulated drain current ID_MD of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages VBIAS with the 50 % threshold-voltage variation (Gaussian distribution) of N-TFT and P-TFT devices is shown in Fig. 6.6. The device dimension of MD device is 80μm/8μm. The gate-to-drain voltage of MD device is set
to zero voltage to be operated in saturation region. The simulated results show that the 50 % threshold-voltage variation with Gaussian distribution of N-TFT and P-TFT devices causes only a variation of 3.84 μA on the drain current ID_MD in the new proposed gate bias voltage generating circuit with threshold-voltage compensation.
Comparing the simulated results of Fig. 6.1 and Fig. 6.6, the new proposed gate bias generating circuit with threshold-voltage compensation can effectively reduce the impact of threshold-voltage variation on the biasing circuit in LTPS process.
6.4. Experimental Results
The new proposed gate bias generating circuit with threshold-voltage compensation has been fabricated in a 8-μm LTPS technology. Fig. 6.7 shows the chip photo of the new proposed gate bias generating technique with threshold-voltage compensation. The test chip size of the new proposed gate bias generating circuit with threshold-voltage compensation circuit is 517 × 389 μm2 in 8-μm LTPS technology. The averaged power consumption of proposed gate bias generating circuit with threshold-voltage compensation is only 47 μW under the supply voltage of 10 V. In this work, the definitions of mean value and variation (%) of currents in these measured results are adopted as sample4 of four LPTS N-TFT devices in different panel locations, respectively, and the # is a sample number from 1 to 4. The power supply voltage VDD is set to 10 V.
Fig. 6.8 shows the measured dependence of variation (%) on the gate voltage VG
under four LTPS N-TFT devices in different panel locations. The device dimensions of four N-TFT devices are kept at 80μm/8μm in a 8-μm LTPS process. The gate voltages of these samples are biased from 1.3 V to 4.3 V. The gate-to-drain voltage of N-TFT device is set to zero voltage to keep the N-TFT device operated in saturation region. Because the gate-control voltage VGC of the new proposed gate bias
generating circuit is VBIAS+VTH, the gate voltage from 1.3 V to 4.3 V is normalized from 0 V to 3 V. The variation (%) among four LPTS N-TFT devices in different panel locations is decreased from 195 % to 30 %, when the gate voltage is increased from 0 V to 3 V. The measured results have confirmed that the variation (%) of four LPTS N-TFT devices in different panel locations under low gate voltage is large, but that under high gate voltage is low.
The measured dependence of variation (%) on the biasing voltage VBIAS among four LTPS test circuits of the new proposed gate bias generating circuit with threshold-voltage compensation in different panel locations is shown in Fig. 6.9. The variation (%) among four LPTS test circuits in different panel locations is decreased from 73 % to 5 %, when the gate voltage is increased from 0 V to 3 V. Comparing the measured results between Fig. 6.8 and Fig. 6.9, the new proposed gate bias generating technique with threshold-voltage compensation can effectively reduce the impact of threshold-voltage variation on the biasing current or biasing voltage for analog circuits in System-on-Panel (SoP) or System-on-Glass (SoG) applications.
6.5. Discussion
When the referenced current source ID_M4 is realized with ideal referenced current source, the simulated results show that variation of ID_MD is only 0.27 μA under 50 % threshold-voltage variation (Gaussian distribution) of N-TFT and P-TFT devices. In order to achieve the low power consumption and small chip area, the referenced current source ID_M4 in the proposed gate bias voltage generating circuit with threshold-voltage compensation is realized by M3 and M4 devices. Because the voltage VC is dependent on threshold voltages of N-TFT and P-TFT devices, the threshold-voltage variation will cause some variations on the voltage VC and biasing current (ID_M4 and ID_MC) to degrade the performances of the proposed gate bias voltage generating circuit with threshold-voltage compensation. The variation of ID_MD is finally increased from 0.27 μA to 3.84 μA under 50 % threshold voltage variation (Gaussian distribution) of N-TFT and P-TFT devices. In order to reduce the impact of referenced current ID_M4 variation on circuit performance, the M3 and M4
referenced current source can be further replaced by the modified N-TFT
threshold-voltage referenced current source [131]. The complete circuit of the proposed gate bias voltage generating circuit with N-TFT threshold-voltage referenced current source for analog circuit applications in LTPS technology is shown in Fig. 6.10. When the referenced current source ID_M4 is realized with modified N-TFT threshold-voltage referenced current source, the simulated results show that the variation of ID_MD is only 0.36 μA under 50 % threshold-voltage variation (Gaussian distribution) of N-TFT and P-TFT devices, as shown in Fig. 6.11.
Because the threshold voltages of N-TFT devices have the same variation trend in the local panel location, the biasing current ID_MD with modified N-TFT threshold-voltage referenced current source can further reduce the variation on performance of the proposed circuit.
6.6. Summary
A new gate bias generating technique with threshold-voltage compensation has been presented to reduce the impact of threshold-voltage variation on analog circuit performance in LTPS technology. The new proposed gate bias generating circuit with threshold-voltage compensation has been successfully verified in a 8-μm LTPS process. The measured results have confirmed that the impact of threshold-voltage variation on drain current of N-TFT device can be reduced from 30 % to 5 % under biasing voltage of 3 V. The new proposed gate bias generating technique with threshold-voltage compensation can be applied to realize analog circuits in LTPS process for System-on-Panel (SoP) or System-on-Glass (SoG) applications.
Fig. 6.1. The simulated waveforms of N-TFT drain current ID with 50 % threshold-voltage variation of Gaussian distribution under different gate voltages VG
in a 8-μm LTPS process.
Fig. 6.2. The concept of the new proposed gate bias voltage generating technique with threshold-voltage compensation.
Fig. 6.3. The complete circuit of the proposed gate bias voltage generating circuit with threshold-voltage compensation for analog circuits in LTPS technology.
Fig. 6.4. The simulated gate control voltage VGC of the proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages VBIAS.
Fig. 6.5. The simulated gate control current VGC of the proposed gate bias voltage generating circuit with threshold-voltage compensation under the different biasing voltages VBIAS with the 50 % threshold voltage variation (Gaussian distribution) on N-TFT and P-TFT devices.
Fig. 6.6. The simulated drain current ID_MD of the proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages VBIAS with the 50 % threshold voltage variation (Gaussian distribution) of N-TFT and P-TFT devices.
Fig. 6.7. The chip photo of the proposed gate bias generating technique with threshold-voltage compensation fabricated in a 8-μm LTPS process.
Fig. 6.8. The measured dependence of variation (%) on the gate voltage VG among four LTPS N-TFT devices in different panel locations.
Fig. 6.9. The measured dependence of variation (%) on the biasing voltage VBIAS
among four LTPS test circuits of the new proposed gate bias generating technique with threshold-voltage compensation in different panel locations.
Fig. 6.10. The complete circuit of the proposed gate bias voltage generating circuit with modified N-TFT threshold-voltage referenced current source for analog circuits in LTPS technology.
Fig. 6.11. The simulated drain current ID_MD of the proposed gate bias voltage generating circuit with modified N-TFT threshold-voltage referenced current source under different biasing voltages VBIAS with the 50 % threshold voltage variation (Gaussian distribution) of N-TFT and P-TFT devices.
CHAPTER 7
Conclusions and Future Works
This chapter summarizes the main results of this dissertation. Then, some suggestions for the future works about the design and reliability of CMOS analog circuit in low-voltage CMOS processes are also addressed in this chapter.
7.1. Main Results of This Dissertation
Due to the growing popularity of electronic technology, the electronic products are continuously asked to reduce its weight, thickness, and volume. So, the reliability of analog integrated circuit is more and more important. Moreover, with the device dimensions of the integrated circuits scaling down, the operation voltage and gate-oxide thickness of device had also been reduced. However, the extra non-ideal effects of devices have great impact on analog integrated circuit to increase design difficulty, such as the lower operation voltage and thin gate oxide. So the new design technique in low-voltage analog integrated circuit can be developed. The thinner gate oxide of device will cause the reliability problem in nanoscale analog integrated circuit. In this dissertation, a new sub-1-V CMOS bandgap reference and curvature-compensation technique for CMOS bandgap reference circuit with sub-1-V operation, the impact of gate-oxide reliability on CMOS analog amplifier, the impact of gate tunneling current on performances of phase locked loop, and the new gate bias voltage generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process have been presented.
In Chapter 2, a new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm × 106 μm.
The experimental results have shown that, with the minimum supply voltage of 0.85
V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from -10 °C to 120 °C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10 kHz. The new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic NPN and PNP BJT devices in CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-μm CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/°C from 0 °C to 100 °C. With 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz.
In Chapter 3, the influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the non-stacked and stacked structures under analog application in a 130-nm low-voltage CMOS process.
The test conditions of this work include the DC stress, AC stress with DC offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output DC voltage levels, are measured to verify the impact of gate-oxide reliability on circuit performances of the common-source amplifiers with diode-connected active load. The small-signal parameters of the common-source amplifier with the non-stacked diode-connected active load structure are stronger degraded than that with non-stacked diode-connected active load structure due to gate-oxide breakdown under analog and digital applications. The common-source amplifiers with diode-connected active load are not functional operation under digital application due to gate-oxide breakdown. The impact of soft and hard gate-oxide breakdowns on common-source amplifiers with non-stacked and stacked diode-connected active load structures has been analyzed and discussed. The hard breakdown has more serious impact to the common-source amplifiers with diode-connected active load. The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the
DC stress, AC stress with DC offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. A simple equivalent device model of gate-oxide reliability for CMOS devices in analog circuitsis investigated and simulated.
In Chapter 4, the MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated with the sample-and-hold amplifier in a 130-nm CMOS process. After overstress on the MOS switch of SHA with open-loop configuration, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device will degrade the performance of bootstrapped switch technique.
In Chapter 5, the thin gate oxide causes the large gate tunneling leakage in
nanoscale CMOS technology. In this work, the influence of MOS capacitor, as loop filter, with gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated and analyzed. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to
nanoscale CMOS technology. In this work, the influence of MOS capacitor, as loop filter, with gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated and analyzed. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to