Experimental Results

When the SHA with the gate-oxide reliability test circuit is operating in the overstress mode, the input signal VIN is biased to supply voltage, and the control voltage VC is set to supply voltage. In order to observe the circuit performance degradation of the SHA due to the gate-oxide degradation of switch device, the voltage at VCLK node is kept to 2.4 V for accelerating the gate-oxide degradation of switch device. Only the gate-to-drain nodes of the switch MS is overstressed to simulate the switched-capacitor circuit with the bootstrapped technique. The measured results of test circuit are measured with die under test on the printed circuit board (PCB). The time-domain and frequency-domain waveforms are re-evaluated after the gate-oxide overstress on MOS switch. When the time-domain and frequency-domain waveforms are re-evaluated after the gate-oxide overstress on the MOS switch, the signal at VCLK node is applied with clock signal between 0 V to 1.2 V. After overstress time of 5.2 hours, the gate-oxide breakdown has been occurred on switch device. The gate-leakage current (IG_leakage) of switch device is jumped from 330 nA to 80.6 μA under VCLK of 2.4 V due to the gate-oxide breakdown.

Figs. 4.8(a) and 4.8(b) show the frequency-domain (10-MHz sampling frequency at VCLK node and 2-MHz sinusoidal signal at VIN node) and time-domain (10-MHz sampling frequency at VCLK node and 1-MHz sinusoidal signal at VIN node) waveforms at VOUT node under different stress times. A frequency axis is shown till 5MHz because of aliasing by Nyquist criterion. The SFDR of the test circuit is degraded by the gate-oxide breakdown on switch device from 35.62 dB to 30.86 dB, because the gate-oxide breakdown causes extra gate-leakage current across gate oxide of switch device to degrade the circuit performances of SHA with the gate-oxide reliability test circuit. However, the amount of gate-leakage current depends on the gate-oxide breakdown location on switch device. The gate-oxide breakdown location near channel region of switch device (soft breakdown) has a smaller gate-leakage current than that near the drain or source side of switch device (hard breakdown) [82].

4.6. Discussion

In order to investigate the impact of gate-oxide breakdown location (switch device) on performances of switched-capacitor circuit with bootstrapped technique, the prior proposed method [81] can be used to simulate this impact with HSPICE. The gate-oxide breakdown of MOSFET device can be modeled as resistance. Only the gate-to-diffusion (source or drain) breakdown was considered, since it represents the worst-case situation [82], [103]. Breakdown to the channel can be modeled as a superposition of two gate-to-diffusion events. Typical hard breakdown leakage has a close-to-linear I-V curve and an equivalent resistance of ~ 10³-10⁴ Ω. However, typical soft breakdown paths have high non-linear, power law I-V curve and equivalent resistance above 10⁵-10⁶ Ω [82]. The equivalent breakdown resistance (VCLK/IG_leakage) of switch device after overstress is approximate 30 kΩ (hard gate-oxide breakdown) under VCLK of 2.4 V.

The SHA including equivalent breakdown resistors RGD and RGS is shown in Fig.

4.9(a). The simulated frequency-domain (10-MHz sampling frequency at VCLK node and 2-MHz sinusoidal signal at VIN node) and time-domain (10-MHz sampling frequency at VCLK node and 1-MHz sinusoidal signal at VIN node) waveforms of the SHA with equivalent breakdown resistor (RGS and RGD) of 30 kΩ are shown in Figs.

4.9(b) and 4.9(c), respectively. Comparing the simulated (Fig. 4.9(c)) with measured (Fig. 4.8(b)) results, the gate-oxide breakdown on switch device in SHA with the gate-oxide reliability test circuit is near the source side of switch device. The difference between Fig. 4.8(b) and Fig. 4.9(c) is due to the gate-to-channel and gate-to-drain breakdowns on switch device caused the extra gate leakage current in SHA. Only the gate-to-source oxide breakdown on switch device will degrade the performances of SHA. In the sampling mode of SHA, the gate leakage current of switch device is smaller than the charge current (ID) of witch device current. In hold mode of SHA, the extra gate leakage current of will discharge the stored charge in sampling capacitor to degrade the circuit performance of SHA. The relationship between extra gate leakage current and stored charge of sampling capacitor under SHA operated in holding mode can be simple expressed as

_ capacitor, Qholding is a stored charge in sampling capacitor, Vholding is the ideal potential stored in sampling capacitor without oxide breakdown on switch device under hold mode, and IG_leakage is the extra gate leakage current of switch device due to gate-oxide breakdown. When the SHA operated in high sampling frequency, the gate-oxide breakdown on switch device has small impact on circuit performance. Therefore, the proposed SHA with the gate-oxide reliability test circuit can be used to verify the impact of gate-oxide breakdown on switched-capacitor circuit with bootstrapped switch technique.

In order to investigate the impact of soft gate-oxide breakdown on circuit performances of the switched-capacitor circuit with bootstrapped technique, the test circuit with equivalent breakdown resistor RGS of 500 kΩ can be used to model the soft gate-oxide breakdowns on the switch device [82]. The simulated frequency-domain (10-MHz sampling frequency at VCLK node and 2-MHz sinusoidal signal at VIN node) and time-domain (10-MHz sampling frequency at VCLK node and 1-MHz sinusoidal signal at VIN node) waveforms of the SHA with equivalent breakdown resistor RGS of 500 kΩ is shown in Fig. 10. The soft gate-oxide breakdown

on the switch device also degrades the circuit performance of SHA. The soft and hard gate-oxide breakdowns on a CMOS transistor will cause different extra gate leakage currents. The soft gat-oxide breakdown on a transistor causes a smaller extra gate leakage current than that of the hard gate-oxide breakdown in CMOS process [82].

Therefore, the soft and hard gate-oxide breakdowns will have different impact on circuit performances of the SHA. The hard gate-oxide breakdown has more serious impact on circuit performances than soft gate-oxide breakdown on switch device of switched-capacitor circuit with bootstrapped switch technique.

4.7. Summary

The impact of gate-oxide transient overstress on MOS switch with bootstrapped technique has been investigated and analyzed with the sample-and-hold amplifier. The time-domain and frequency-domain waveforms of the SHA after different stress times have been measured. After the gate-oxide overstress, only the gate-to-source oxide breakdown on switch device will degrade the performances of SHA. The overstress time is related to the RC time constant ratio of the sampling and bootstrapping networks in bootstrapped switch technique. The best solution of bootstrapped switch design is that the bootstrapped and sampling networks have same RC delay times to avoid the transient gate-oxide overstress and to achieve the best performance. The hard gate-oxide breakdown has more serious impact on switched-capacitor circuit with bootstrapped technique.

Fig. 4.1. (a) Conceptual schematic and (b) detail circuit implementation of bootstrapped technique for switched-capacitor circuit.

Fig. 4.2. Simulated waveforms of gate-oxide transient overstress event in switched-capacitor circuit with bootstrapped technique.

Fig. 4.3. The dependence of the different sampling capacitors on output voltage waveform in the switched-capacitor circuit with the bootstrapped technique.

Fig. 4.4. The dependence of the input/sampling frequency ratio on maximum transient voltage in the switched-capacitor circuit with the bootstrapped technique.

Fig. 4.5. The complete circuit of sample-and-hold amplifier with the gate-oxide reliability test circuit, where the control device MC is used to control the drain voltage of the switch device MS for reliability test.

(a) (b)

Fig. 4.6. (a) Chip micrograph and (b) layout view of the sample-and-hold amplifier with the gate-oxide reliability test circuit realized in a 130-nm CMOS process.

Fig. 4.7. The simulated frequency-domain and time-domain waveforms of the sample-and-hold amplifier with the gate-oxide reliability test circuit under normal operation.

(a)

(b)

Fig. 4.8. The measured frequency-domain and time-domain waveforms of the sample-and-hold amplifier with the gate-oxide reliability test circuit. (a) Overstress time = 0 hour, and (b) overstress time = 5.2 hours.

(a)

(b)

(c)

Fig. 4.9. (a) The sample-and-hold amplifier with the gate-oxide reliability test circuit including equivalent breakdown resistors RGD and RGS. The simulated frequency-domain and time-domain waveforms of the test circuit with equivalent breakdown resistance (b) RGD and (c) RGS of 30 kΩ , respectively.

Fig. 4.10. The sample-and-hold amplifier with the gate-oxide reliability test circuit including equivalent breakdown resistors RGS. The simulated frequency-domain and time-domain waveforms of the test circuit with equivalent breakdown resistors RGS of 500 kΩ.

CHAPTER 5

Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

In nanoscale CMOS technology, the thin gate oxide causes the large gate tunneling leakage. In this work, the influence of gate tunneling leakage in MOS capacitor, as loop filter, on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated and analyzed. The basic PLL with second-order loop filter is used to observe the impact of gate tunneling leakage on performance degradation of PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to observe this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter. Overview on the prior designs of compensation techniques to reduce the gate tunneling leakage on MOS capacitor in loop filter of PLL is also provided in this work.

5.1. Background

The reduction of power consumption has become increasingly important to portable products, such as mobile phone, notebook, and flash memory. In general, the most common and efficient way to reduce the power consumption in CMOS very large scale integrated circuits (VLSI) is to reduce the power-supply voltage. To reduce the power consumption in CMOS VLSI systems, the standard supply voltage has been scaled down from 2.5 V to 1 V. The gate-oxide thickness of the MOS transistor becomes thinner to reduce normal operation voltage (power-supply voltage). This result causes large gate tunneling leakage (gate leakage current), which relates to

gate-oxide thickness. For the digital circuits, the gate tunneling leakage results in the high stand-by power consumption. For analog circuits, it degrades the circuit accuracy [105]. Therefore, to suppress gate tunneling leakage effect is a very important design issue in analog circuit design in naoscale CMOS process [26], [106].

In PLL, the capacitor of loop filter needs a large capacitance to make PLL stable.

The MOS capacitor has a larger capacitance than other structure under the same chip area to reduce the fabrication cost, but it has a large gate tunneling leakage on MOS capacitor of loop filter to degrade the PLL performances in advanced CMOS technology. Recently, some researches of circuit design technique to compensate the gate tunneling leakage of MOS capacitor in PLL have been reported in nanoscale CMOS process [107]-[112]. The MOS capacitor with thick-oxide device has a less gate tunneling leakage [107]. The capacitor with multi-metal structure was used to replace MOS capacitor to avoid the gate tunneling leakage [108]. The thin oxide MOS capacitor with opamp compensated technique is developed to reduce the gate tunneling leakage effect [109]-[111]. The loop filter with gate tunneling leakage compensator was also developed [112]. However, the impact of gate tunneling leakage on PLL performance was not detailed investigation and analysis in advanced CMOS technology.

In this work, the influence of gate tunneling leakage on performances of the phase locked loop (PLL) in nanoscale CMOS technology is investigated and analyzed in a 90-nm 1-V CMOS process [113]. The normal operating voltage of MOSFET device is only 1 V in such a 90-nm CMOS process. The gate tunneling leakage of MOS capacitance is simulated by SPICE with BSIM4 model. The BSIM4 model has been included with the gate tunneling leakage effect [27], [114], [115]. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL.

Overview on the prior designs of compensation techniques to reduce the gate tunneling leakage on MOS capacitor in loop filter of PLL is also provided in this work.

5.2. Phase Locked Loop

PLL is a necessary building block in many very large scale integrated circuits (VLSI). The demand for low-jitter PLLs has become especially strong in advance nanoscale CMOS process. A PLL is basically an oscillator whose frequency is locked onto some frequency component of an input signal. Fig. 5.1 shows the basic PLL with second-order low-pass loop filter structure [116]. A PLL consists of a phase/frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider (divided by N). The negative feedback system synchronizes the internal signal (FBACK) which is from the frequency divider to the external reference signal (FREF) by comparing their phases. The PFD develops two output control signals, which are proportional to the phase errors. The purpose of the charge pump is to convert the logic states of PFD into analog signals suitable for controlling VCO which varies the frequency of the output signal by charging or discharging the loop filter. In the loop filter, extra poles and zeros should be introduced to filter out high frequency signals from the PFD and the charge pump.

The PLL is “locked” when the phase difference between FREF and FBACK is constant.

Therefore, the phase of FREF and FBACK are aligned and the frequency of the output signals is N-times of the input reference signal (FREF). The loop filter developed with second-order low-pass filter is widely used in PLL design to improve the stability and to suppress the high-frequency noise. The on-chip capacitor is usually designed with MOS capacitor to reduce the fabrication cost in second-order PLL. The second-order loop filter structure can be realized with PMOS and NMOS devices, respectively, as shown in Fig. 5.2.

5.3. MOS Capacitor With Gate Tunneling Leakage Model

In PLL, the capacitor of loop filter needs a large capacitance to make PLL stable.

The MOS capacitor has a larger capacitance than other structure under the same chip area to reduce the fabrication cost, but it has a large gate tunneling leakage on MOS capacitor of loop filter to degrade the PLL performances in advanced CMOS technology. The MOSFET device with gate tunneling leakage model is proposed by Hu [27], [114]. The gate tunneling leakage of MOSFET device is composed of several components, as shown in Fig. 5.3(a): 1. gate-to-substrate (bulk) tunneling leakage Igb, 2. tunneling leakage between gate and source-drain extension (SDE) overlap Igso and

Igdo, and 3. gate-to-channel tunneling leakage Igc, which in turn is partition between the source and drain nodes (Igcs and Igcd). The significance of each component varies with the operation mode of the MOSFET device. They are determined by carrier conduction processes: electron conduction-band tunneling (ECB), electron valence-band tunneling (EVB), and hole valance-band tunneling (HVB), as shown Fig.

5.3(b). Each mechanism is dominant or important in different regions of operation for NMOS and PMOS devices, as shown in Table 5.1. For each mechanism, the gate tunneling leakage density can be modeled as [27], [114],

( )(¹ ) reference oxide thickness at which all the parameter that defaults to 1, and Vaux is an auxiliary function which approximates the density of tunneling carriers. α, β, and γ are the physical parameters defined by device technology. The Vg is the gate voltage of MOSFET device, ntox is a fitting parameter that defaults to 1, and Vox is the voltage across the oxide of MOSFET device.

The MOS capacitor is usually operated in strong inversion region for CMOS circuit design. In equation (5.1), the gate tunneling leakage density strongly depends on the oxide thickness, device dimension, and voltage across the oxide of MOSFET.

Fig. 5.4 shows the dependence of gate tunneling leakage on the gate voltage of different threshold-voltage NMOS and PMOS capacitors in a 90-nm CMOS technology. The capacitance of different MOS capacitors is designed with 85.172 pf under the gate voltage of 0.492 V. The normal operating voltage of MOSFET device is only 1 V, and the typical oxide thickness of MOSFET device is only 2.33 nm in a 90-nm CMOS process. The NMOS capacitor has larger gate tunneling leakage than PMOS capacitor.

The reason is that electron tunneling ECB is the dominant component of gate tunneling leakage in NMOS device, whereas it is the HVB in PMOS device. As the barrier height for HVB (4.5 eV) is significantly larger than that for ECB (3.1 eV), the results in the much lower gate tunneling leakage for PMOS device [115]. The

summary of gate tunneling leakage per unit area under different threshold-voltage NMOS and PMOS capacitors in a 90-nm CMOS process is shown Table 5.2. The thin-oxide NMOS device with the low threshold voltage has larger gate tunneling leakage than other devices in a 90-nm CMOS process.

5.4. Effect of Gate Tunneling Leakage in MOS Capacitor on Performances of PLL Circuit

In this work, the PLL with second-order low-pass loop filter is used to investigate the impact of gate tunneling leakage of MOS capacitor on PLL performances. The design parameters and simulated results of second-order PLL in a 90-nm CMOS process are shown in Table 5.3. The results of second-order PLL are simulated by HSPICE with a 90-nm CMOS SPICE model. In order to compare the impact of gate tunneling leakage of MOS capacitor on PLL performances, the loop filter (C1, C2, and R1) in second-order PLL is developed and simulated with ideal capacitor and resistor in Table 5.3. In this work, the different types and oxide thicknesses of MOS devices are used to realize the MOS capacitor and to investigate the impact of gate tunneling leakage on PLL performances. The C1 and C2 capacitors of low-pass loop filter in PLL, as shown in Fig. 5.4, are replaced by different oxide thickness MOS capacitors to investigate the impact of gate tunneling leakage on PLL performances. The capacitances of different MOS capacitors C1 and C2 are 85.172 pf and 8.782 pf under gate voltage of 0.492 V, respectively, for second-order PLL design.

Fig. 5.5 shows the simulated control voltage (VCTRL) transition waveform to find the locked time under different oxide thickness MOS capacitors in second-order PLL.

The thin-oxide MOS capacitors (1-V NMOS and PMOS) have longer locked time and cause larger ripple voltage Vr than thick-oxide MOS capacitor (1.8-V NMOS), when the phase difference between FREF and FBACK is constant. The simulated dependence of static phase error Δt on the time under different oxide thickness MOS capacitors in second-order PLL is shown in Fig. 5.6. The thin-oxide MOS capacitors (1-V NMOS and PMOS) cause larger static phase error Δt than thick-oxide MOS capacitor (1.8-V NMOS) in second-order PLL. The simulated jitter under different oxide thickness MOS capacitors in second-order PLL is shown in Fig. 5.7. The thin-oxide MOS

capacitors (1-V NMOS and PMOS) cause larger jitter than thick-oxide MOS capacitor (1.8-V NMOS) in second-order PLL, due to the large ripple voltage at VCTRL node. The dependence of jitter and ripple voltage on different input signal frequencies under different oxide thickness devices is shown in Fig. 5.8. The high input signal frequency FREF has a small jitter, and low input signal frequency has a large jitter in second-order PLL with gate tunneling leakage.

5.5. Discussion

In general, the capacitance of MOS capacitor C1 is larger than that of MOS capacitor C2 in second-order PLL design, as shown in Fig. 3. Because the capacitance of MOS capacitor is proportion to device dimension and oxide thickness, the gate

In general, the capacitance of MOS capacitor C1 is larger than that of MOS capacitor C2 in second-order PLL design, as shown in Fig. 3. Because the capacitance of MOS capacitor is proportion to device dimension and oxide thickness, the gate