Chapter 7. Conclusions and Future Works
7.2. Future Works
In this dissertation, a new sub-1-V CMOS bandgap reference and curvature-compensation technique for CMOS bandgap reference circuit with sub-1-V operation, the impact of gate-oxide reliability on CMOS analog amplifier, the impact of gate tunneling current on performances of phase locked loop, and the new gate bias voltage generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process have been presented. However, the gate-oxide breakdown of MOSFET device modeled as resistance can be only used to investigate the impact of gate-oxide breakdown on circuit performances. In addition, the more accurate gate-oxide breakdown model of MOSFET devices is required in simulation or Engineering Design Automation (EDA) tool to improve the circuit reliability in advanced CMOS technology. Therefore, the more accurate gate-oxide breakdown model of MOSFET devices must be developed in the future.
Due to the trends of system on chip (SoC) and CMOS technology, the more analog circuits will be designed with low operation voltage in advanced CMOS processes and integrated in a single chip. Thus, not only the bandgap reference circuits but also other circuits, such as OPAMP (operational amplifier), ADC (analog-to-digital converter), and so on, must be designed with low operation voltage in advanced CMOS processes. Such design topic still continues to the future research.
Due to the SoP or SoG applications, more analog and digital circuits will be integrated on glass substrate. However, the threshold-voltage variation of TFT device
will degrade the circuit performance on glass substrate. In order to achieve the high performance and reliability smart plane application, such design topic still continues to the future research.
References
[1] Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2006.
[2] R. S. Scott, N. A. Dumin, T. W. Hughes, D. J. Dumin, and B. T. Moore,
“Properties of high-voltage stress generated traps in thin silicon oxide,” IEEE Trans. Electron Devices, vol. 43, pp. 1133-1143, July 1996.
[3] H. Iwai and H. S. Momose, “Ultra-thin gate oxides-performance and reliability,”
in IEDM. Tech. Dig., 1998, pp. 163-166.
[4] A. M. Yassine, H. E. Nariman, M. McBride, M. Uzer, and K. R. Olasupo, “Time dependent breakdown of ultrathin gate oxide,” IEEE Trans. Electron Devices, vol.
47, pp. 1416-1420, July 2000.
[5] J. S. Suehle, “Ultrathin gate oxide reliability: physical models, statistics, and characterization,” IEEE Trans. Electron Devices, vol. 49, pp. 958-971, June 2002.
[6] Y. Leblebici, “Design consideration for CMOS digital circuits with improved hot-carrier reliability,” IEEE J. Solid-State Circuits, vol. 31, pp. 1014-1024, July 1996.
[7] J.-Y. Choi, P.-K. Ko, and C. Hu, “Hot-carrier-induced MOSFET degradation under AC stress,” IEEE Electron Device Lett., vol. 8, pp. 333-335, Aug. 1987.
[8] H. Kufluoglu and M. A. Alam, “Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 1120-1130, May 2006.
[9] S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress,”
IEEE Trans. Electron Devices, vol. 53, pp. 1583-1592, July 2006.
[10] B. C. Paul, K. Kunhyuk, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” IEEE Electron Device Lett., vol. 26, pp. 560-562, Aug. 2005.
[11] N. K. Jha, P. S. Reddy, D. K. Sharma, and V. R. Rao, “NBTI degradation and its impact for analog circuit reliability,” IEEE Trans. Electron Devices, vol. 52, pp.
2069-2615, Dec. 2005.
[12] J. H. Stathis, “Percolation models for gate oxide breakdown,” J. Appl. Phys., vol.
86, pp. 5757-5766, Nov. 1999.
[13] R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, and H. E. Maes, “A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides,” in IEDM. Tech. Dig., pp. 863-866, 1995.
[14] H.-C. Lin, D.-Y. Lee, C.-Y. Lee, T.-S. Chao, T.-Y. Huang, and T. Wang, “New insights into breakdown modes and their evolution in ultra-thin gate oxide,” in Proc. Int. Symp. VLSI Tech., pp. 37-40, 2001.
[15] M. Depas, T. Nigam, and M. Heyns, “Soft breakdown of ultra-thin gate oxide layers,” IEEE Trans. Electron Devices, vol. 43, pp. 1499-1504, Sept. 1996.
[16] E. R. Minaami, S. B. Kuusinen, E. Rosenbaum, P. K. Ko, and C. Hu,
“Circuit-level simulation of TDDB failure in digital CMOS circuit,” IEEE Trans.
Semiconductor Manufacturing, vol. 8, pp. 370-374, Aug. 1995.
[17] K.-H. Lee, B. R. Jones, C. Burke, L. V. Tran, J. A. Shimer, and M. L. Chen,
“Lightly doped drain structure for advanced CMOS (Twin-Tub IV),” in IEDM Tech. Dig., 1985, 242-245.
[18] T.-Y. Huang, I-W. Wu, and J. Y. Chen, “A MOS transistor with self-aligned polysilicon source-drain,” IEEE Electron Device Lett., vol. 7, pp. 314-316, May 1986.
[19] M.-L. Chen, C.-W. Leung, W. T. Cochran, W. Hungling, C. Dziuba, and T. Yang,
“Suppression of hot-carrier effects in submicrometer CMOS technology,” IEEE Trans. Electron Devices, vol. 35, pp. 2210-2220, Dec. 1988.
[20] I.-C. Chen, J. Y. Choi, and C. Hu, “The effect of channel hot-carrier stressing on gate-oxide integrity in MOSFETs,” IEEE Trans. Electron Devices, vol. 35, pp.
2253-2258, Dec. 1988.
[21] K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MOS devices,” J. Appl. Phys., vol. 48, pp.
2004-2014, May 1977.
[22] M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for p-MOSFETs,” in IEDM Tech. Dig., 2003, pp. 345-348.
[23] S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, “A comprehensive framework for predictive modeling of negative bias temperature instability,” in Proc. Int. Reliab. Phys. Symp., 2004, pp. 273-282.
[24] H. Kufluoglu and M. A. Alam, “Theory of interface-trap-induced NBTI
degradation for reduced cross section MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 1120-1130, May 2006.
[25] S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A. P. Chandrakasan,
“Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS” IEEE J. Solid-State Circuits, vol. 39, pp. 501-510, Mar.
2004.
[26] C.-H. Choi, K.-Y. Nam, Z. Yu, and R. W. Dutton, “Impact of gate direct tunneling current on circuit performance: a simulation study,” IEEE Trans. Electron Devices, vol. 48, pp. 2823-2829, Dec. 2001.
[27] W.-C. Lee and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” in Proc. IEEE Int. Symp. VLSI Tech., 2000, pp. 198-201.
[28] Y.-S. Lin, C.-C. Wu, C.-S. Chang, R.-P. Yang, W.-M. Chen, J.-J. Liaw, and C. H.
Diaz, “Leakage scaling in deep submicron CMOS for SoC,” IEEE Trans.
Electron Devices, vol. 49, pp. 1034-1041, Jun. 2002.
[29] M.-J. Chen, H.-T. Huang, C.-S. Hou, and K.-N. Yang, “Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFETs,” IEEE Electron Device Lett., vol. 19, pp. 134-136, Apr. 1998.
[30] K.-N. Yang, H-T. Huang, M.-J. Chen, Y.-M. Lin, M.-C. Yu, S.-M. Jang, C.-H. Yu, and M.-S. Liang, “Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs,” IEEE Trans. Electron Devices, vol.
48, pp. 1159-1164, June 2001.
[31] M. Rosar, B. Leroy, and G. Schweeger, “A new model for the description of gate voltage and temperature dependence of gate induced drain leakage (GIDL) in the low electric field region,” IEEE Trans. Electron Devices, vol. 47, pp. 154-159, Jan. 1999.
[32] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance,” IEEE Trans. Electron Devices, vol. 49, pp. 826-831, May 2002.
[33] Z. M. Rittersma, M. Vertregt, W. Deweerd, S. van Elshocht, P. Srinivasan, and E.
Simoen, “Characterization of mixed-signal properties of MOSFETs with high-k (SiON/HfSiON/TaN) gate stacks,” IEEE Trans. Electron Devices, vol. 53, pp.
1216-1225, May 2006.
[34] C. R. Manoj and V. R. Rao, “Impact of high-K gate dielectrics on the device and circuit performance of nanoscale FinFETs,” IEEE Electron Device Lett., vol. 28, pp. 295-297, Apr. 2007.
[35] M. Ismail and T. Fiez, Analog VLSI Signal and Information Processing. New York: McGraw-Hill, 1994.
[36] B. J. Blalock, P. E. Allen, and G. A. R. Rincon-Mora, “Designing 1-V op amps using standard digital CMOS technology”, IEEE Trans. Circuits Syst. II, vol. 45, pp. 769-780, July 1998.
[37] E. Sanchez-Sinencio and A. G. Andreou, Low Voltage/Low Power Integrated Circuits and Systems. IEEE Press, 1999.
[38] J. Mulder, A. C. van der Woerd, W. A. Serdijn, and A. H. M. van Roermund,
“Application of back gate in MOS weak inversion translinear circuits”, IEEE Trans. Circuits Syst. I, vol. 42, pp. 958-962, Nov. 1995.
[39] J. Ramirez-Angulo, S. C. Choi, and G. G. Altamirano, “Low voltage circuits building blocks using multiple input floating gate transistors”, IEEE Trans.
Circuits Syst. I, vol. 42, pp. 971-974, Nov. 1995.
[40] P. Hasler and T. S. Lande, “Overview of floating gate devices, circuits and systems”, IEEE Trans. Circuits Syst. II, vol. 48, pp. 1-3, Jan. 2001.
[41] Y. Berg, T. S. Lande, O. Naess, and H. Gundersen “Ultra low voltage floating gate transconductance amplifiers”, IEEE Trans. Circuits Syst. II, vol. 48, pp.
32-44, Jan. 2001.
[42] F. Munoz, A. Torralba, R. G. Carvajal, J. Tombs, and J. Ramirez-Angulo,
“Floating gate biased tunable low voltage linear transconductor and its applications to gm–C filter design”, IEEE Trans. Circuits Syst. II, vol. 48, pp.
106-110, Jan. 2001.
[43] J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, “Low voltage CMOS op amp with rail to rail input and output signal swing for continuous time signal processing using multiple input floating gate transistors”, IEEE Trans.
Circuits Syst. II, vol. 48, pp. 111-116, January 2001.
[44] P. Hasler, T. Stanford, and B. A. Minch, “A second order section built from autozeroing floating gate amplifiers”, IEEE Trans. Circuits Syst. II, vol. 48, pp.
116-120, Jan. 2001.
[45] D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York: John Wiley & Sons, Inc., 1997.
[46] C. T. Shah, “Characterization of the metal oxide semiconductor transistors”, IEEE Transactions on Electron Devices, vol. 11, pp. 324-345, July 1964.
[47] R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: Mc-Graw Hill, 1990.
[48] D. Seo, H. Dabag, Y.a Guo, M. Mishra, and G. H. McAllister,
“High-voltage-tolerant analog circuits design in deep sub-micron CMOS technologies,” IEEE Trans. Circuits Syst. I, in press, 2007.
[49] B. Kaczer, R. Degraeve, M. Rasras, K. V. D. Mieroop, P. J. Roussel, and G.
Groeseneken, “Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability,” IEEE Trans. Electron Devices, vol. 49, pp. 500-506, Mar. 2002.
[50] B. Kaczer and G. Groesenken, “Potential vulnerability of dynamic CMOS logic to soft gate oxide breakdown,” IEEE Electron Device Lett., vol. 24, pp. 742-744, Dec. 2003.
[51] H. Yang, J. S. Yuan, T. Liu, and E. Xiao, “Effect of gate-oxide breakdown on RF performance,” IEEE Trans. Device Materials Reliabil., vol. 3, pp. 93-97, Sept.
2003.
[52] R. Rodriguze, J. H. Stathis, B. P. Kinder, S. Kowalczyk, C. T. Chaung, R. V. Joshi, G. Northorp, K. Bernstein, and A. J. Bhavnagarwala, “The impact of gate-oxide breakdown on SRAM stability,” IEEE Electron Device Lett., vol. 23, pp. 559-561, Sept. 2002.
[53] “The International Technology Roadmap for Semiconductors,” Semiconductor Industry Association, 2004.
[54] Y. Jiang and E. K. F. Lee, “Design of low-voltage bandgap reference using transimpedance amplifier,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 552-555, June 2000.
[55] K. N. Leung and K. T. Mok, “A sub-1-V 15-ppm/°C CMOS bandgap reference without requiring low threshold voltage device,” IEEE J. Solid-State Circuits, vol.
37, pp. 526-529, Apr. 2002.
[56] J. Doyle, Y. J. Lee, Y.-B. Kim, H. Wilsch, and F. Lombardi, “A CMOS subbandgap reference circuit with 1-V power supply voltage,” IEEE J.
Solid-State Circuits, vol. 39, pp. 252-255, Jan. 2004.
[57] P. Malcovati, F. Maloberti, M. Pruzzi, and C. Fiocchi, “Curvature compensated
BiCMOS bandgap with 1-V supply voltage,” IEEE J. Solid-State Circuits, vol. 36, pp. 1076-1081, July 2001.
[58] H. Neuteboom, B. M. J. Kup, and M. Janssens, “A DSP-based hearing instrument IC,” IEEE J. Solid-State Circuits, vol. 32, pp. 1790-1806, Nov. 1997.
[59] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K.
Sakui, “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE J.
Solid-State Circuits, vol. 34, pp. 670-674, May 1999.
[60] G. Giustolisi, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, pp. 151-154, Jan. 2003.
[61] A.-J. Annema, “Low-power bandgap references featuring DTMOSTs,” IEEE J.
Solid-State Circuits, vol. 34, pp. 949-955, July 1999.
[62] G. A. Rincon-Mora and P. E. Allen, “A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference,” IEEE J. Solid-State Circuits, vol. 33, pp.
1551-1554, Oct. 1998.
[63] F. S. Graells and J. L. Huertas, “Sub-1-V proportional-to-absolute temperature reference,” IEEE J. Solid-State Circuits, vol. 38, pp. 84-88, Jan. 2003.
[64] M.-D. Ker, J.-S Chen, and C.-Y. Chu, “A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device,” in Proc.
IEEE Int. Symp. Circuits and Systems, 2004, pp. 41-44.
[65] G. Giustolisi and G. Palumbo, “A detailed analysis of power-supply noise attenuation in bandgap voltage references,” IEEE Trans. Circuits Syst. I, vol. 50, pp. 185-197, Feb. 2003.
[66] S. R. Lewis and A. P. Brokaw, “Curvature correction of bipolar bandgap reference,” U.S. Patent 4808908, Feb. 28, 1989.
[67] M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement. Oxford Publishers, pp.287-289, 2001.
[68] B.-S. Song and P. R. Gray, “A precision curvature-compensated CMOS bandgap voltage reference,” IEEE J. Solid-State Circuits, vol. 18, no. 6, pp. 634-643, Dec.
1983.
[69] I. Lee, G. Kim, and W. Kim, “Exponential curvature-compensated BiCMOS bandgap voltage references,” IEEE J. Solid-State Circuits, vol. 29, pp. 1396-1403, Nov. 1994.
[70] M. Gunawan, G. C. M. Meijer, J. Fonderie, and J. H. Huijsing, “A curvature-corrected low-voltage bandgap voltage reference,” IEEE J. Solid-State
Circuits, vol. 28, pp. 667-670, Jun. 1993.
[71] S. R. Lewis and A. P. Brokaw, “Curvature correction of bipolar bandgap voltage reference,” U.S. Patent 4808908, Feb. 28, 1989.
[72] K. N. Leung, K. T. Moke, and C. Y. Leung, “A 2-V 23- A curvature-compensated CMOS bandgap voltage reference,” IEEE J. Solid-State Circuits, vol. 38, pp. 561-564, Mar. 2003.
[73] K.-M. Tham and K. Nagaraj, “A low supply voltage high PSRR voltage reference in CMOS process,” IEEE J. Solid-State Circuits, vol. 30, pp. 586-590, May 1995.
[74] M.-D. Ker, J.-S. Chen, and C.-Y. Chu, “New curvature-compensation technique for CMOS bandgap voltage reference with sub-1-V operation,” in Proc. IEEE Int.
Symp. Circuits and Systems, 2005, pp. 3861-3864.
[75] G. A. Rincon-Mora, Voltage Reference-From Diodes to Precision High-Order Bandgap Circuits. New York: Wiley, 2002.
[76] K. Eriguchi and M. Niwa, “Stress polarity dependence of the activation energy in time-dependent dielectric breakdown of thin gate oxides,” IEEE Electron Device Lett., vol. 19, pp. 339-401, Dec. 1998.
[77] B. P. Linder, S. Lombardo, J. H. Stathis, A. Vayshenker, and D. Frank, “Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics,” IEEE Electron Device Lett., vol. 23, pp. 661-663, Nov. 2002.
[78] B. Kaczer, R. Degraeve, E. Augendre, M. Jurczak, and G. Groeseneken,
“Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns,” in Proc. European Solid-State Device Research, 2003, pp.
75-78.
[79] E. Xiao, J. S. Yuan, T. Liu, and H. Yang, “CMOS RF and DC reliability subject to hot carrier stress and oxide soft breakdown,” IEEE Trans. Device Materials Reliabil., vol. 4, pp. 92-98, Mar. 2004.
[80] B. E. Weir, P. J. Silverman, D. Monroe, K. S. Krisch, M. A. Alam, G. B. Alers, T.
W. Sorsch, G. L. Timp, F. Baumann, C. T. Liu, Y. Ma, and D. Hwang, “Ultra-thin gate dielectrics: They breakdown, but do they fail,” in IEDM Tech. Dig., 1997, pp.
73-76.
[81] M. A. Alam, B. E. Weir, P. J. Siverman, Y. Ma, and D. Hwang, “The statistical distribution of percolation resistance as a probe into the mechanics of ultra-thin oxide breakdown,” in IEDM Tech. Dig., 2000, pp. 529-533.
[82] R. Degraeve, B. Kaczer, A. D. Keersgieter, and G. Groeseneken, “Relation
between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications,” IEEE Trans. Device Materials Reliabil., vol. 1, pp. 163-169, Sept. 2001.
[83] B. Kaczer, F. Crupi, R. Degraeve, P. Roussel, C. Ciofi, and G. Groesenken,
“Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stress,” in IEDM Tech. Dig., 2002, pp. 171-174.
[84] A. M. Abo and P. R. Gray, “A 1.5 V, 10 bits, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
[85] J.-B. Park, S.-M. Yoo, S.-W. Kim, Y.-J. Cho, and S.-H. Lee, “A 10-b 150-Msample/s 1.8 V 123-mW CMOS A/D converter with 400-MHz input bandwidth,” IEEE J. Solid-State Circuits, vol. 39, pp. 1335-1337, Aug. 2004.
[86] B. Serneels, T. Piessens, M. Steyaert, and W. Dehaene, “A high-voltage output driver in a standard 2.5 V 0.25 μm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 146-155.
[87] M.-D. Ker and S.-L. Chen, “Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3xVDD input tolerance by using 1xVDD devices and single VDD power supply,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2005, pp. 524-525.
[88] J.-S. Chen and M.-D. Ker, “Impact of MOSFET gate-oxide reliability in CMOS operational amplifiers in a 130-nm low-voltage CMOS process,” in Proc. IEEE Int. Reliability Physics Symp., 2005, pp. 423-430.
[89] A. Aevllan and W. H. Kraustschneider, “Impact of soft and hard breakdown on analog and digital circuits,” IEEE Trans. Device Materials Reliabil., vol. 4, pp.
676-680, Dec. 2004.
[90] M. Nafria, J. Sune, D. Yelamos, and X. Aymerich, “Degradation and breakdown of thin silicon dioxide films under dynamic electrical stress,” IEEE Trans.
Electron Devices, vol. 43, pp. 2215-2225, Dec. 1996.
[91] R. Rodriguez, J. H. Stathis, and B. P. Linder, “A model for gate-oxide breakdown in CMOS inverters,” IEEE Electron Device Lett., pp. 114-116, Dec. 2003.
[92] “Topical issue on oxide reliability,” Semicond. Sci. Technol., vol. 5, 2000.
[93] B. Kaczer, F. Crupi, R. Degraeve, P. Roussel, C. Ciofi, and G. Groesenken,
“Observation of hot-carrier-induced nFET gate- oxide breakdown in dynamically
stress,” in IEDM Tech. Dig., 2002, pp. 171-174.
[94] D. Aksin, M. A. Shyoukh, and F. Maloberti, “Switch bootstrapping for precise sampling beyond supply voltage,” IEEE J. Solid-State Circuits, vol. 41, pp.
1938-1943, Aug. 2006.
[95] S. Yao, X. Wu, and X. Yan, “Modifications for reliability of bootstrapped switches in low voltage switched-capacitor circuits,” in Proc. IEEE Int. Electron Devices and Solid-State Circuits, 2005, pp. 449-452.
[96] S.-M. Yoo, J.-B. Park, H.-S. Yang, H.-H. Bae, K.-H. Moon, H.-J. Park, S.-H. Lee, and J.-H. Kim, “A 10 b 150 MS/s 123 mW 0.18 μm CMOS pipelined ADC,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 326-497.
[97] L. Wang and S. H. K. Embabi, “Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper,” IEEE J. Solid-State Circuits, vol. 38, pp.
1411-1415, Aug. 2003.
[98] A. Baschirotto, “A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 Ms/s,” IEEE Trans. Circuits Syst. II, vol. 48, pp.
394-399, Apr. 2001.
[99] D.-Y. Chang and U.-K. Moon, “A 1.4-V 10-bit 25-MS/spiplined ADC using opamp-rest switching technique,” IEEE J. Solid-State Circuits, vol. 38, pp.
1401-1404, Aug. 2003.
[100] L. Dai and R. Harjani, “CMOS switched-op-amp-based sample-and-hold circuit,”
IEEE J. Solid-State Circuits, vol. 35, pp. 109-113, Jan. 2000.
[101] J.-S. Chen and M.-D. Ker, “Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process,” in Proc.
IEEE Int. Reliability Physics Symp., 2006, pp. 705-706.
[102] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation,” IEE Electronics Letters, vol. 35, pp. 8-9, Jan. 1999.
[103] X. Li, J. Qin, B. Huang, X. Zhang, and J. B. Bernstein, “A SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits,” IEEE Trans.
Device Materials Reliabil., vol. 6, pp. 247-257, Jun. 2006.
[104] C. Yu and J. S. Yuan, “MOS RF reliability subject to dynamic voltage stress—modeling and analysis,” IEEE Trans. Electron Devices, vol. 52, pp.1751-1758, Aug. 2005,
[105] W. K. Henson, N. Yang, S. Kubicek, E. M. Vogel, J. J. Wortman, K. De Meyer, and A. Maem, “Analysis of leakage currents and impact on off-state power
consumption for CMOS technology in the 100-nm regime,” IEEE Trans.
Electron Devices, vol. 47, pp. 1393-1400, July 2000.
[106] M. Drazdziulis and P. Lrsson-Edefors, “A gate leakage reduction strategy for future CMOS circuits,” in Proc. IEEE European Solid-State Circuits Conf., 2003, pp. 317-320.
[107] K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura, and M. Yamashina, “A 0.10μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO,” in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 213-216.
[108] R. Holzer, “A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.
Papers, 2002, pp. 272-274.
[109] R. Maley, “Method and apparatus for tunneling leakage current compensation,”
US Patent 6744303, Jun. 2004.
[110] K. Ho, “Method and apparatus for gate current compensation,” US Patent 6696881, Feb. 2004.
[111] C.-N. Chuang and S.-I. Liu, “A 1V phase locked loop with leakage compensation in 0.13μm CMOS Technology,” IEICE Trans. Electron., vol. E89-C, pp. 295-299, Mar. 2006.
[112] Y. Frans, N. Nguyen, B. Daly, Y. Wang, D. Kim, T. Bystrom, D. Olarte, and K.
Donnelly, “A 1-4 Gbps quad transceiver cell using PLL with gate current leakage compensator in 90nm CMOS,” in Proc. IEEE Int. Symp. VLSI Circuit, 2004, pp.
134-137.
[113] J.-S. Chen and M.-D. Ker, “Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology,” in Proc. IEEE Int.
Reliability Physics Symp., 2007, pp. 664-665.
[114] K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source-drain partition,” in IEDM Tech. Dig., 2000, pp. 815-817.
[115] C.-H. Choi, K.-H. Oh; J.-S. Goo; Z. Yu, and R. W. Dutton, “Direct tunneling current model for circuit simulation,” in IEDM Tech. Dig., 2000, pp. 735-738.
[116] D. H. Wolaver, Phase-Locked Loop Circuit Design. NJ: Prentice Hall, 1991.
[117] Y. Tang, M. Ismail, and S. Bibyk, “Adaptive Miller capacitor multiplier for