Non-Opamp Base Compensation Technique

where the I2 is the gate tunneling leakage of dummy MOS capacitor CC. Therefore, the gate tunneling leakage of loop filter with MOS capacitor in PLL can be compensated by this technique.

Fig. 5.11 re-draws another PLL with opamp base gate tunneling leakage compensation circuit [111]. This compensation technique uses a thick gate-oxide device (or MIM capacitor) realized the capacitor C2 of loop filter and the opamp as gate tunneling compensation circuit. In the locked state of PLL, the voltage at VCTRl

node and gate voltage of MOS capacitor C1 are almost equal. The opamp uses to keep that the voltage at VCTRL node and the gate voltage of MOS capacitor C1 have the same voltage potential. The gate tunneling leakage of MOS capacitor C1 can be compensated by opamp. Therefore, the gate tunneling leakage of MOS capacitor C1 in PLL can be compensated by this technique.

5.6.3. Non-Opamp Base Compensation Technique

Fig. 5.12 re-draws another PLL with non-opamp base gate tunneling leakage base compensation circuit [112]. The gate tunneling leakage compensation circuit consists of a charge pump CPC, MOS capacitors of CCP and CCN, and current source PCOMP. When there is a leakage at node VCTRL, the duration of the PFD output “UP”

signal is longer than the PFD output “DN” signal. The gate tunneling leakage compensation circuit integrates this error at node VCTRL which controls the compensating current Icomp to compensate the gate tunneling leakage IGTL,LF of MOS capacitors C1 and C2. To avoid the gate tunneling leakage of MOS capacitors CCP and CCN, the MOS capacitors CCP and CCN are realized with thick gate-oxide devices. The area penalty is insignificant since the capacitance value of MOS capacitors CCP and CCN is far less than that of MOS capacitors C1 and C2. Since the capacitance value of MOS capacitors CCP and CCN does not have to be precise, they are built using both PMOS and NMOS thick gate-oxide device to address strong-inversion turn-on voltage issues. In the locked state of PLL, the relationship between compensating current

ICOMP and total gate tunneling gate leakage IGTL,LF of MOS capacitors C1 and C2 in

where Δt is the static phase error of PLL due to the gate tunneling leakage of loop filter, VTH is the threshold voltage of PCOMP device, COX is the gate oxide capacitance per unit area of PCOMP device.

5.6.4. Capacitor Multiplier

Fig. 5.13 re-draws loop filter with voltage-mode capacitor multiplier [117]. The capacitor C1 of loop filter is multiplier by miller capacitor theory. A non-inverting CMOS opamp is used as the amplifier input stage, followed by an inverting unity gain buffer for the negative voltage gain, as shown in Fig. 13. The effective input capacitance in Fig. 13 is given by

( )

⁴ implement capacitor C1 is therefore reduced by 67% [15]. Because the gate tunneling leakage and capacitance of MOS capacitor are proportion to device dimension, the smaller device dimension of MOS capacitor has smaller gate tunneling leakage that larger device dimension of MOS capacitor. Therefore, the impact of gate tunneling leakage on performance of PLL will be reduced by using the voltage-mode capacitor multiplier in advanced CMOS technology.

Fig. 5.14 re-draws current-mode PLL with current-mode capacitor multiplier [118], [119]. Compared with conventional charge-pump PLL, the main difference is it utilizes a current-mode filter that drives the current controlled oscillator (ICO) directly.

The charge pump current ICP is a portion of the control current of the ICO, as referred to self-biased technique [120]. The transfer function can be expressed by

( )

¹

The transconductance gm is degenerated by the resistor RG without compromising the tuning range. So the effective loop capacitance is given by

1

Ceff =MC , (5.11) M α 1

=α

− , (5.12) The left-hand plane (LHP) zero guarantees the stability of the current-mode loop filter.

The α/(α-1) term of current-mode loop filter should be designed larger than zero. So the current-mode loop filter is similar to the conventional loop filter in PLL. The self-biased current-mode filter is biased by PLL loop, then the power and die size could be further saved [118], [119]. Because the gate tunneling leakage and capacitance of MOS capacitor are proportion to device dimension, the smaller device dimension of MOS capacitor has smaller gate tunneling leakage that larger device dimension of MOS capacitor. Therefore, the impact of gate tunneling leakage on performance of PLL will be reduced by using the current-mode capacitor multiplier in advanced CMOS technology.

However, using extra components to realize the loop filter by using the capacitor multiplier technique will increase the extra noise sources to degrade the performances of PLL in advanced CMOS technology.

5.7. Summary

The influence of gate tunneling leakage in MOS capacitor on circuit performances of second-order PLL has been analyzed and investigated in a 90-nm CMOS process. The locked time, static phase error, and jitter of second-order PLL are degraded by gate tunneling leakage of MOS capacitor in loop filter. The high input

signal frequency can be used to reduce the impact of gate tunneling leakage on performance of second-order PLL in nanoscale CMOS technology. The PMOS device with high threshold voltage and thick oxide thickness can be used to realize the MOS capacitor in the loop filter for achieving low-jitter and low-cost second-order PLL.

Overview on the prior designs of compensation techniques to reduce the gate tunneling leakage on MOS capacitor in loop filter of PLL is also provided in this work. Considering the chip area, circuit performance and fabrication cost in advanced CMOS technology, the capacitor multiplier technique is a good choice to realize the MOS capacitor in second-order PLL.

Table5.1

Major Gate Tunneling Leakage Mechanisms of MOSFET Device in Nanoscale CMOS Technology [27]

Table 5.2

The Summary of Gate Tunneling Leakage Per Unit Area under Different Threshold-Voltage NMOS and PMOS Capacitors in a 90-nm CMOS Process

Table 5.3

The Design Parameters and Simulated Results of Second-Order PLL in a 90-nm CMOS Process

Fig. 5.1. The basic phase locked loop with second-order low-pass loop filter structure.

(a)

(b)

Fig. 5.2. The second-order loop filter realized with (a) PMOS and (b) NMOS capacitors.

(a)

(b)

Fig. 5.3. (a) Gate tunneling leakage in a thin oxide MOSFET device, and (b) carrier tunneling process with different barrier voltage.

Fig. 5.4. The simulated dependence of gate tunneling leakage on different threshold-voltage NMOS and PMOS capacitors under different gate voltages in a 90-nm CMOS technology.

Fig. 5.5. The simulated control voltage waveforms to find the locked time under MOS capacitors with different oxide thicknesses in second-order PLL.

Fig. 5.6. The simulated voltage waveforms to find the static phase error (Δt) under MOS capacitors with different oxide thicknesses in second-order PLL.

Fig. 5.7. The simulated voltage waveforms to find the jitter under MOS capacitors with different oxide thicknesses in second-order PLL.

Fig. 5.8. The dependence of different input signal frequencies on jitter and ripple voltage under different oxide thickness devices in the MOS capacitor.

Fig. 5.9. The schematic of second-order PLL including gate tunneling leakage effect.

Fig. 5.10. The schematic of PLL with opamp base gate tunneling leakage compensation circuit by only using thin gate-oxide device [109].

Fig. 5.11. The schematic of PLL with opamp base gate tunneling leakage compensation circuit [111].

Fig. 5.12. The schematic of PLL with non-opamp base gate tunneling leakage compensation circuit [112].

Fig. 5.13. The loop filter with voltage-mode capacitor multiplier [117].

Fig. 5.14. The schematic of current-mode PLL with current-mode capacitor multiplier technique [118], [119].

CHAPTER 6

New Gate Bias Voltage Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process

A new proposed gate bias voltage generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon LTPS thin-film transistors (TFTs) is proposed. The new proposed gate bias voltage generating circuit with threshold-voltage compensation has been successfully verified in a 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5%

under biasing voltage of 3 V. The new proposed gate bias voltage generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by LTPS process on glass substrate for active matrix LCD (AMLCD) panel.

6.1. Background

Low-temperature poly-Si LTPS thin-film transistors (TFTs) have attracted a lot of attentions in the applications with the integrated on-panel peripheral circuits for active-matrix liquid crystal display (AMLCD) and active-matrix light emitting diodes (AMOLEDs) [121]-[123]. Recently, LTPS AMLCDs integrated with driving and control circuits on glass substrate have been realized in some portable systems, such as mobile phone, digital camera, notebook, etc. In the near future, the AMLCD fabricated in LTPS process is promising toward System-on-Panel (SoP) or System-on-Glass (SoG) applications, especially for achieving a compact, low-cost, and low-power display system [124].

The LCD data driver contains shifter registers, level shifters, digital-to-analog converters (DACs), and output buffers. The biasing circuit is a critical circuit block for analog circuits on LCD panel to achieve low power consumption, high speed, and high resolution. However, the poly-Si TFT device suffers from significant variation in its threshold voltage, owing to the nature of poly silicon crystal growth in LTPS process. The threshold-voltage variation across a 2.7-inch panel was about 300 mV [125]. The variation could even be as large as 1 V in some high-performance TFT devices across a large substrate area [126]. The threshold-voltage variations of TFT devices will cause large mismatches on the biasing voltages and currents in analog circuits to result in non-uniformity of performances among analog circuits over the whole panel. The design with threshold-voltage compensation for analog circuits on glass substrate is a very important challenge for SoP applications. The design technique with switches and capacitors under multi-phase clock operation were usually used to compensate the threshold-voltage variation among TFT devices in LTPS AMLCDs [127]-[129]. Some design technique with switch and capacitor under multi-phase clock operation had used to reduce the offset voltage of analog buffer in LTPS process [127]. In LTPS technology, the on-panel output buffers with a pair of n-type and p-type TFT devices immune to the mismatch of threshold voltage were also reported [128], [129]. The mismatch of threshold voltage can be compensated by a holding capacitor or the mathematical product of voltage gain. Besides, the threshold-voltage-shift compensation technique was used to compensate the threshold-voltage variation for differential amplifier in analog circuits [130].

However, those techniques [127]-[130] only emphasize the impact of threshold-voltage variation on offset voltage of analog buffers on glass substrate. The biasing circuit with threshold-voltage compensation for analog circuits in LTPS process is not yet reported in the literature.

In this paper, a method to reduce the influence of threshold-voltage variation on the gate bias voltage generating circuit for analog circuits on glass substrate is proposed. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5%

under biasing voltage of 3 V. The new proposed biasing technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented in LTPS process for active matrix LCD (AMLCD) panel.

6.2. Impact of Threshold-Voltage Variation on TFT I-V Characteristics

In general, the TFT devices on glass substrate are usually designed in saturation region for analog circuit applications. The small-signal gain and frequency response of analog circuits in LTPS process are determined by transconductance (gm) and output resistance (ro) of TFT devices. The small-signal parameters of transconductance (gm) and output resistance (ro) in TFT devices can be expressed as, respectively, where μ is the mobility of carrier, L denotes the effective channel length, W is the effective channel width, Cox is the gate oxide capacitance per unit area, VTH is the threshold voltage of TFT device, VGS is the gate-to-source voltage of TFT device, VA

is the Early voltage, and ID is the drain current of TFT device. Comparing equations (6.1) and (6.2), the drain current ID is the major factor for analog circuits in LTPS process. Therefore, the performances of analog circuits in LTPS process are dominated by drain current of TFT device. The drain current ID of TFT device operated in saturation region can be expressed as

1 2

The channel-length modulation of TFT device is not included in equation (6.3). The threshold voltage (VTH) of TFT device is an important parameter in equation (6.3), so the threshold-voltage variation among TFT devices will cause the variation on drain currents of TFT devices to degrade the circuit performances in analog circuits on glass substrate. How to design a stable biasing circuit with threshold-voltage compensation to reduce non-uniformity of performances in analog circuits over the whole panel in LTPS process is an important design challenge.

The HSPICE with Monte Carlo Analysis can be used to simulate and analyze the impact of threshold-voltage variation on drain current of TFT device. The threshold-voltage variation of TFT device on glass substrate can be modeled by Gaussian distribution. The simulated waveforms of N-TFT drain current ID with 50

% threshold-voltage variation of Gaussian distribution under different gate voltages VG in a 8-μm LTPS process is shown in Fig. 6.1. The dimension of N-TFT device is 80μm/8μm. The gate voltage is biased from 1.3 V to 4.3 V. In order to confirm that N-TFT device is operated in saturation region, the drain voltage of N-TFT device is also biased from 1.3 V to 4.3 V to keep gate-to-drain voltage of zero volt. The simulated result shows that the N-TFT device with 50 % threshold-voltage variation of Gaussian distribution causes the drain current with a variation as large as 22 μA in LTPS process. Therefore, the large variations on drain currents of TFT devices will cause large mismatches on the biasing voltages and currents in analog circuits to further result in non-uniformity of performances in analog circuits over the whole panel. For the System-on-Plane (SoP) applications, to reduce the impact of threshold-voltage variation on performance among analog circuits in LTPS process is a very important design challenge.

6.3. New Proposed Gate Bias Voltage Generating Technique With Threshold-Voltage Compensation

6.3.1 Design Concept

The new proposed gate bias voltage generating technique with threshold-voltage compensation is illustrated in Fig. 6.2. The biasing current ID_MC is a small current used to bias the MC device operated in weak inversion region. When the MC device operated in weak inversion region, the gate control voltage VGC can be written as

_

GC BIAS TH MC

V ≅V +V , (6.4) where VTH_MC is the threshold-voltage of MC device, and VBIAS is the applied biasing voltage. The drain current ID_MD of MD device can be expressed as

2 drawn with the same device dimension. The threshold-voltage difference between MC

and MD devices can be reduced as small as possible by symmetrical and compact layout in an adjacent location. Therefore, the equation (6.5) can be further rewritten as

The drain current ID_MD of MD device can become independent on the threshold voltage and dominated by the VBIAS voltage. The new proposed gate bias voltage generating technique with threshold-voltage compensation does not need any extra clock signal and capacitor to reduce the impact of threshold-voltage variation on the biasing circuit for analog circuits in LTPS processes.

6.3.2.Circuit Implementation

The complete circuit of the proposed gate bias voltage generating technique with threshold-voltage compensation for analog circuit applications in LTPS technology is shown in Fig. 6.3. The new proposed gate bias voltage generating circuit with threshold-voltage compensation is formed with M1, M2, M3, M4, M5, and M6 devices.

The M1, M2, M5, and M6 devices form the current mirror. In order to reduce the power consumption and chip area of the new proposed gate bias voltage generating circuit, the M3 and M4 devices are used to realize the referenced current source. The M3 and M4 devices are operated in saturation region o generate a biasing current through the current mirror of M1, M2, M5, and M6 devices to bias MC device operated in weak inversion region. The voltage VC can be expressed as

_ 3 _ 4

( ) ( )

₄³ generating circuit. The biasing current ID_M4 and ID_MC can be written as, respectively,

( )

² especially designed much larger than one to reduce the impact of biasing current (ID_M4) variation on gate control voltage (VGC) of the new proposed gate bias voltage generating circuit.

The simulated gate control voltage VGC of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages VBIAS is shown in Fig. 6.4. The typical threshold voltage of N-TFT device in 8-μm LTPS process is approximately 1.3 V. The VBIAS voltage is biased from 0 V to 3V. The gate control voltage VGC is changed from 1.3 V to 4.3 V. The gate control voltage VGC of the new proposed gate bias voltage generating circuit with threshold-voltage compensation is approximately VBIAS+VTH_MC. The HSPICE with Monte Carlo Analysis is used to verify the function of the new proposed gate bias voltage generating circuit with threshold-voltage compensation in LTPS technology.

The simulated gate control current VGC of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under the different biasing voltages VBIAS with the 50 % threshold voltage variation (Gaussian distribution) of N-TFT and P-TFT devices is shown in Fig. 6.5. The variation on gate control voltage VGC, which can be used to compensate the threshold-voltage variation of TFT device in LTPS process, is 0.675 V. The simulated drain current ID_MD of the new proposed gate bias voltage generating circuit with threshold-voltage compensation under different biasing voltages VBIAS with the 50 % threshold-voltage variation (Gaussian distribution) of N-TFT and P-TFT devices is shown in Fig. 6.6. The device dimension of MD device is 80μm/8μm. The gate-to-drain voltage of MD device is set

to zero voltage to be operated in saturation region. The simulated results show that the 50 % threshold-voltage variation with Gaussian distribution of N-TFT and P-TFT devices causes only a variation of 3.84 μA on the drain current ID_MD in the new proposed gate bias voltage generating circuit with threshold-voltage compensation.

Comparing the simulated results of Fig. 6.1 and Fig. 6.6, the new proposed gate bias generating circuit with threshold-voltage compensation can effectively reduce the impact of threshold-voltage variation on the biasing circuit in LTPS process.

6.4. Experimental Results

The new proposed gate bias generating circuit with threshold-voltage compensation has been fabricated in a 8-μm LTPS technology. Fig. 6.7 shows the chip photo of the new proposed gate bias generating technique with threshold-voltage compensation. The test chip size of the new proposed gate bias generating circuit with threshold-voltage compensation circuit is 517 × 389 μm² in 8-μm LTPS technology. The averaged power consumption of proposed gate bias generating circuit with threshold-voltage compensation is only 47 μW under the supply voltage of 10 V. In this work, the definitions of mean value and variation (%) of currents in these measured results are adopted as sample4 of four LPTS N-TFT devices in different panel locations, respectively, and the # is a sample number from 1 to 4. The power supply voltage VDD is set to 10 V.

Fig. 6.8 shows the measured dependence of variation (%) on the gate voltage VG

under four LTPS N-TFT devices in different panel locations. The device dimensions of four N-TFT devices are kept at 80μm/8μm in a 8-μm LTPS process. The gate voltages of these samples are biased from 1.3 V to 4.3 V. The gate-to-drain voltage of N-TFT device is set to zero voltage to keep the N-TFT device operated in saturation

under four LTPS N-TFT devices in different panel locations. The device dimensions of four N-TFT devices are kept at 80μm/8μm in a 8-μm LTPS process. The gate voltages of these samples are biased from 1.3 V to 4.3 V. The gate-to-drain voltage of N-TFT device is set to zero voltage to keep the N-TFT device operated in saturation

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