Chapter 5. Impact of Gate Tunneling Leakage on Performances of Phase Locked
5.3. MOS Capacitor With Gate Tunneling Leakage Model
In PLL, the capacitor of loop filter needs a large capacitance to make PLL stable.
The MOS capacitor has a larger capacitance than other structure under the same chip area to reduce the fabrication cost, but it has a large gate tunneling leakage on MOS capacitor of loop filter to degrade the PLL performances in advanced CMOS technology. The MOSFET device with gate tunneling leakage model is proposed by Hu [27], [114]. The gate tunneling leakage of MOSFET device is composed of several components, as shown in Fig. 5.3(a): 1. gate-to-substrate (bulk) tunneling leakage Igb, 2. tunneling leakage between gate and source-drain extension (SDE) overlap Igso and
Igdo, and 3. gate-to-channel tunneling leakage Igc, which in turn is partition between the source and drain nodes (Igcs and Igcd). The significance of each component varies with the operation mode of the MOSFET device. They are determined by carrier conduction processes: electron conduction-band tunneling (ECB), electron valence-band tunneling (EVB), and hole valance-band tunneling (HVB), as shown Fig.
5.3(b). Each mechanism is dominant or important in different regions of operation for NMOS and PMOS devices, as shown in Table 5.1. For each mechanism, the gate tunneling leakage density can be modeled as [27], [114],
( )(1 ) reference oxide thickness at which all the parameter that defaults to 1, and Vaux is an auxiliary function which approximates the density of tunneling carriers. α, β, and γ are the physical parameters defined by device technology. The Vg is the gate voltage of MOSFET device, ntox is a fitting parameter that defaults to 1, and Vox is the voltage across the oxide of MOSFET device.
The MOS capacitor is usually operated in strong inversion region for CMOS circuit design. In equation (5.1), the gate tunneling leakage density strongly depends on the oxide thickness, device dimension, and voltage across the oxide of MOSFET.
Fig. 5.4 shows the dependence of gate tunneling leakage on the gate voltage of different threshold-voltage NMOS and PMOS capacitors in a 90-nm CMOS technology. The capacitance of different MOS capacitors is designed with 85.172 pf under the gate voltage of 0.492 V. The normal operating voltage of MOSFET device is only 1 V, and the typical oxide thickness of MOSFET device is only 2.33 nm in a 90-nm CMOS process. The NMOS capacitor has larger gate tunneling leakage than PMOS capacitor.
The reason is that electron tunneling ECB is the dominant component of gate tunneling leakage in NMOS device, whereas it is the HVB in PMOS device. As the barrier height for HVB (4.5 eV) is significantly larger than that for ECB (3.1 eV), the results in the much lower gate tunneling leakage for PMOS device [115]. The
summary of gate tunneling leakage per unit area under different threshold-voltage NMOS and PMOS capacitors in a 90-nm CMOS process is shown Table 5.2. The thin-oxide NMOS device with the low threshold voltage has larger gate tunneling leakage than other devices in a 90-nm CMOS process.
5.4. Effect of Gate Tunneling Leakage in MOS Capacitor on Performances of PLL Circuit
In this work, the PLL with second-order low-pass loop filter is used to investigate the impact of gate tunneling leakage of MOS capacitor on PLL performances. The design parameters and simulated results of second-order PLL in a 90-nm CMOS process are shown in Table 5.3. The results of second-order PLL are simulated by HSPICE with a 90-nm CMOS SPICE model. In order to compare the impact of gate tunneling leakage of MOS capacitor on PLL performances, the loop filter (C1, C2, and R1) in second-order PLL is developed and simulated with ideal capacitor and resistor in Table 5.3. In this work, the different types and oxide thicknesses of MOS devices are used to realize the MOS capacitor and to investigate the impact of gate tunneling leakage on PLL performances. The C1 and C2 capacitors of low-pass loop filter in PLL, as shown in Fig. 5.4, are replaced by different oxide thickness MOS capacitors to investigate the impact of gate tunneling leakage on PLL performances. The capacitances of different MOS capacitors C1 and C2 are 85.172 pf and 8.782 pf under gate voltage of 0.492 V, respectively, for second-order PLL design.
Fig. 5.5 shows the simulated control voltage (VCTRL) transition waveform to find the locked time under different oxide thickness MOS capacitors in second-order PLL.
The thin-oxide MOS capacitors (1-V NMOS and PMOS) have longer locked time and cause larger ripple voltage Vr than thick-oxide MOS capacitor (1.8-V NMOS), when the phase difference between FREF and FBACK is constant. The simulated dependence of static phase error Δt on the time under different oxide thickness MOS capacitors in second-order PLL is shown in Fig. 5.6. The thin-oxide MOS capacitors (1-V NMOS and PMOS) cause larger static phase error Δt than thick-oxide MOS capacitor (1.8-V NMOS) in second-order PLL. The simulated jitter under different oxide thickness MOS capacitors in second-order PLL is shown in Fig. 5.7. The thin-oxide MOS
capacitors (1-V NMOS and PMOS) cause larger jitter than thick-oxide MOS capacitor (1.8-V NMOS) in second-order PLL, due to the large ripple voltage at VCTRL node. The dependence of jitter and ripple voltage on different input signal frequencies under different oxide thickness devices is shown in Fig. 5.8. The high input signal frequency FREF has a small jitter, and low input signal frequency has a large jitter in second-order PLL with gate tunneling leakage.
5.5. Discussion
In general, the capacitance of MOS capacitor C1 is larger than that of MOS capacitor C2 in second-order PLL design, as shown in Fig. 3. Because the capacitance of MOS capacitor is proportion to device dimension and oxide thickness, the gate tunneling leakage of the MOS capacitor C2 is larger than the capacitor C1. The schematic of Fig. 3 can be simplified to that of Fig. 5.9, where the current ICP is the charge pump current, and the current IGTL, LF is the total gate tunneling leakage of MOS capacitors C1 and C2. The charge pump current ICP, which is controlled by the phase difference between FREF and FBACK signals through PFD, is a constant current source. The effective charge current IC of MOS capacitors C1 and C2 can be expressed as
,
C CP GTL LF
I =I −I . (5.2) In order to reach locked state (phase difference between FREF and FBACK is constant), the second-order PLL needs a setting time for system stability. Therefore, the locked time of second-order PLL is increased due to gate tunneling leakage of MOS capacitor.
In locked state, the dependence of gate tunneling leakage on ripple voltage Vr in second-order PLL can be written by proportion to gate tunneling leakage. The large gate tunneling current of MOS
capacitor will cause large ripple voltage at VCTRL node in second-order PLL. In equation (5.3), the ripple voltage Vr is proportion to the period of input signal FREF, so the low input signal frequency causes a large ripple voltage, and the high input signal frequency causes a small ripple voltage in second-order PLL, as shown in Fig. 8. The dependence of gate tunneling leakage on jitter of second-order PLL can be expressed as
where the KVCO (Hz/V) is the gain of voltage-controlled oscillator VCO. The large ripple voltage ΔVr cause the large jitter in second-order PLL. The dependence of gate tunneling leakage on static phase error Δt of second-order PLL can be expressed as
, In order to reduce the static phase error in second-order PLL, the charge pump current should be designed with large constant current.
As a result, how to design a low-jitter and low-cost second-order PLL in nanoscale CMOS technology is a very important design issue. Comparing the Table 5.2, Figs. 5.5, 5.6, 5.7, and 5.8, the PMOS device with high threshold voltage or thick oxide thickness is a good solution to realize the MOS capacitor of loop filter in low-cost second-order PLL. The new circuit design technique for compensating the gate tunneling leakage of MOS capacitor in low jitter and low-cost PLL is also needed to be developed in nanoscale CMOS technique.
5.6. Overview on the Prior Designs of Loop Filter With Gate Tunneling Leakage Compensation Technique in PLL
5.6.1. Capacitor Structure
The MOS capacitor of loop filter in PLL can be designed with thick gate-oxide
device or metal-insulator-metal capacitor (MIM) to reduce the impact of gate tunneling leakage on performance of PLL [107], [108]. Because the gate tunneling leakage of MOS capacitor is proportion to oxide thickness, the thick gate-oxide device has smaller gate tunneling leakage than thin gate-oxide device in nanoscale CMOS technology. However, the threshold voltage of thick gate-oxide device is higher than that of thin gate-oxide device in nanoscale CMOS process. Thick gate-oxide device needs a high voltage level to reach strong inversion region. This consequently would cause headroom issues and limit the tunneling range of VCO in PLL. These problems can be solved by using thick gate-oxide with multi threshold voltage device in naonoscale CMOS process. The capacitor with MIM structure is no gate tunneling leakage problem. However, MIM capacitor needs more silicon area than MOS capacitor under the same capacitance in nanoscale CMOS technology.
Therefore, the capacitor of loop filter in PLL realized with MIM capacitor will increase the fabrication cost.
5.6.2. Opamp Base Compensation Technique
Fig. 5.10 re-draws the PLL with opamp base gate tunneling leakage compensation circuit [109]. The gate tunneling leakage compensation circuit consists with dummy MOS capacitor CC, M1, M2, and opamp to compensate the gate tunneling leakage of MOS capacitors C1 and C2. The MOS capacitors of C1, C2, and CC are realized with thin gate-oxide device. The M1 and M2 devices form the current mirror.
The dimension of MOS capacitor CC is smaller than that of MOS capacitors C1 and C2. Because the gate voltage of MOS capacitor C1 is not equal to voltage at VCTRL node in track state of PLL, the locked time of PLL should be increased by using the gate tunneling leakage compensation technique. In the locked state of PLL, the voltage at VCTRl node and gate voltage of MOS capacitor C1 are almost equal. The opamp with negative feedback can be used to keep that the V+ and Vctrl nodes have the same voltage potential. Because the gate tunneling leakage and capacitance of MOS capacitor are proportion to device dimension and oxide thickness, the relationship between I1, I2, and total gate tunneling gate leakage IGTL,LF of MOS capacitors C1 and C2 in loop filter can be expressed by
( ) ( )
where the I2 is the gate tunneling leakage of dummy MOS capacitor CC. Therefore, the gate tunneling leakage of loop filter with MOS capacitor in PLL can be compensated by this technique.
Fig. 5.11 re-draws another PLL with opamp base gate tunneling leakage compensation circuit [111]. This compensation technique uses a thick gate-oxide device (or MIM capacitor) realized the capacitor C2 of loop filter and the opamp as gate tunneling compensation circuit. In the locked state of PLL, the voltage at VCTRl
node and gate voltage of MOS capacitor C1 are almost equal. The opamp uses to keep that the voltage at VCTRL node and the gate voltage of MOS capacitor C1 have the same voltage potential. The gate tunneling leakage of MOS capacitor C1 can be compensated by opamp. Therefore, the gate tunneling leakage of MOS capacitor C1 in PLL can be compensated by this technique.
5.6.3. Non-Opamp Base Compensation Technique
Fig. 5.12 re-draws another PLL with non-opamp base gate tunneling leakage base compensation circuit [112]. The gate tunneling leakage compensation circuit consists of a charge pump CPC, MOS capacitors of CCP and CCN, and current source PCOMP. When there is a leakage at node VCTRL, the duration of the PFD output “UP”
signal is longer than the PFD output “DN” signal. The gate tunneling leakage compensation circuit integrates this error at node VCTRL which controls the compensating current Icomp to compensate the gate tunneling leakage IGTL,LF of MOS capacitors C1 and C2. To avoid the gate tunneling leakage of MOS capacitors CCP and CCN, the MOS capacitors CCP and CCN are realized with thick gate-oxide devices. The area penalty is insignificant since the capacitance value of MOS capacitors CCP and CCN is far less than that of MOS capacitors C1 and C2. Since the capacitance value of MOS capacitors CCP and CCN does not have to be precise, they are built using both PMOS and NMOS thick gate-oxide device to address strong-inversion turn-on voltage issues. In the locked state of PLL, the relationship between compensating current
ICOMP and total gate tunneling gate leakage IGTL,LF of MOS capacitors C1 and C2 in
where Δt is the static phase error of PLL due to the gate tunneling leakage of loop filter, VTH is the threshold voltage of PCOMP device, COX is the gate oxide capacitance per unit area of PCOMP device.
5.6.4. Capacitor Multiplier
Fig. 5.13 re-draws loop filter with voltage-mode capacitor multiplier [117]. The capacitor C1 of loop filter is multiplier by miller capacitor theory. A non-inverting CMOS opamp is used as the amplifier input stage, followed by an inverting unity gain buffer for the negative voltage gain, as shown in Fig. 13. The effective input capacitance in Fig. 13 is given by
( )
4 implement capacitor C1 is therefore reduced by 67% [15]. Because the gate tunneling leakage and capacitance of MOS capacitor are proportion to device dimension, the smaller device dimension of MOS capacitor has smaller gate tunneling leakage that larger device dimension of MOS capacitor. Therefore, the impact of gate tunneling leakage on performance of PLL will be reduced by using the voltage-mode capacitor multiplier in advanced CMOS technology.Fig. 5.14 re-draws current-mode PLL with current-mode capacitor multiplier [118], [119]. Compared with conventional charge-pump PLL, the main difference is it utilizes a current-mode filter that drives the current controlled oscillator (ICO) directly.
The charge pump current ICP is a portion of the control current of the ICO, as referred to self-biased technique [120]. The transfer function can be expressed by
( )
1The transconductance gm is degenerated by the resistor RG without compromising the tuning range. So the effective loop capacitance is given by
1
Ceff =MC , (5.11) M α 1
=α
− , (5.12) The left-hand plane (LHP) zero guarantees the stability of the current-mode loop filter.
The α/(α-1) term of current-mode loop filter should be designed larger than zero. So the current-mode loop filter is similar to the conventional loop filter in PLL. The self-biased current-mode filter is biased by PLL loop, then the power and die size could be further saved [118], [119]. Because the gate tunneling leakage and capacitance of MOS capacitor are proportion to device dimension, the smaller device dimension of MOS capacitor has smaller gate tunneling leakage that larger device dimension of MOS capacitor. Therefore, the impact of gate tunneling leakage on performance of PLL will be reduced by using the current-mode capacitor multiplier in advanced CMOS technology.
However, using extra components to realize the loop filter by using the capacitor multiplier technique will increase the extra noise sources to degrade the performances of PLL in advanced CMOS technology.
5.7. Summary
The influence of gate tunneling leakage in MOS capacitor on circuit performances of second-order PLL has been analyzed and investigated in a 90-nm CMOS process. The locked time, static phase error, and jitter of second-order PLL are degraded by gate tunneling leakage of MOS capacitor in loop filter. The high input
signal frequency can be used to reduce the impact of gate tunneling leakage on performance of second-order PLL in nanoscale CMOS technology. The PMOS device with high threshold voltage and thick oxide thickness can be used to realize the MOS capacitor in the loop filter for achieving low-jitter and low-cost second-order PLL.
Overview on the prior designs of compensation techniques to reduce the gate tunneling leakage on MOS capacitor in loop filter of PLL is also provided in this work. Considering the chip area, circuit performance and fabrication cost in advanced CMOS technology, the capacitor multiplier technique is a good choice to realize the MOS capacitor in second-order PLL.
Table5.1
Major Gate Tunneling Leakage Mechanisms of MOSFET Device in Nanoscale CMOS Technology [27]
Table 5.2
The Summary of Gate Tunneling Leakage Per Unit Area under Different Threshold-Voltage NMOS and PMOS Capacitors in a 90-nm CMOS Process
Table 5.3
The Design Parameters and Simulated Results of Second-Order PLL in a 90-nm CMOS Process
Fig. 5.1. The basic phase locked loop with second-order low-pass loop filter structure.
(a)
(b)
Fig. 5.2. The second-order loop filter realized with (a) PMOS and (b) NMOS capacitors.
(a)
(b)
Fig. 5.3. (a) Gate tunneling leakage in a thin oxide MOSFET device, and (b) carrier tunneling process with different barrier voltage.
Fig. 5.4. The simulated dependence of gate tunneling leakage on different threshold-voltage NMOS and PMOS capacitors under different gate voltages in a 90-nm CMOS technology.
Fig. 5.5. The simulated control voltage waveforms to find the locked time under MOS capacitors with different oxide thicknesses in second-order PLL.
Fig. 5.6. The simulated voltage waveforms to find the static phase error (Δt) under MOS capacitors with different oxide thicknesses in second-order PLL.
Fig. 5.7. The simulated voltage waveforms to find the jitter under MOS capacitors with different oxide thicknesses in second-order PLL.
Fig. 5.8. The dependence of different input signal frequencies on jitter and ripple voltage under different oxide thickness devices in the MOS capacitor.
Fig. 5.9. The schematic of second-order PLL including gate tunneling leakage effect.
Fig. 5.10. The schematic of PLL with opamp base gate tunneling leakage compensation circuit by only using thin gate-oxide device [109].
Fig. 5.11. The schematic of PLL with opamp base gate tunneling leakage compensation circuit [111].
Fig. 5.12. The schematic of PLL with non-opamp base gate tunneling leakage compensation circuit [112].
Fig. 5.13. The loop filter with voltage-mode capacitor multiplier [117].
Fig. 5.14. The schematic of current-mode PLL with current-mode capacitor multiplier technique [118], [119].
CHAPTER 6
New Gate Bias Voltage Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process
A new proposed gate bias voltage generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon LTPS thin-film transistors (TFTs) is proposed. The new proposed gate bias voltage generating circuit with threshold-voltage compensation has been successfully verified in a 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5%
under biasing voltage of 3 V. The new proposed gate bias voltage generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by LTPS process on glass substrate for active matrix LCD (AMLCD) panel.
6.1. Background
Low-temperature poly-Si LTPS thin-film transistors (TFTs) have attracted a lot of attentions in the applications with the integrated on-panel peripheral circuits for active-matrix liquid crystal display (AMLCD) and active-matrix light emitting diodes (AMOLEDs) [121]-[123]. Recently, LTPS AMLCDs integrated with driving and control circuits on glass substrate have been realized in some portable systems, such as mobile phone, digital camera, notebook, etc. In the near future, the AMLCD fabricated in LTPS process is promising toward System-on-Panel (SoP) or System-on-Glass (SoG) applications, especially for achieving a compact, low-cost, and low-power display system [124].
The LCD data driver contains shifter registers, level shifters, digital-to-analog converters (DACs), and output buffers. The biasing circuit is a critical circuit block for analog circuits on LCD panel to achieve low power consumption, high speed, and high resolution. However, the poly-Si TFT device suffers from significant variation in
The LCD data driver contains shifter registers, level shifters, digital-to-analog converters (DACs), and output buffers. The biasing circuit is a critical circuit block for analog circuits on LCD panel to achieve low power consumption, high speed, and high resolution. However, the poly-Si TFT device suffers from significant variation in