Chapter 3. Impact of Gate-Oxide Reliability on CMOS Analog Amplifiers Circuit
3.2. Operational Amplifier
3.2.5. Effect of Hard and Soft Gate-Oxide Breakdown on
3.2.5.1. DC Stress
After oxide breakdown, the measured output voltage swing waveform of operational amplifier with the two-stage structure after DC stress, as shown in Fig.
3.20, is shown in Fig. 3.34. Based on the prior proposed method [81], [90], the gate-oxide breakdown of MOSFET device can be modeled as resistance. Only the gate-to-diffusion (source or drain) breakdown was considered, since these represent the worst-case situation. Breakdown to the channel can be modeled as a superposition of two gate-to-diffusion events. Typical hard breakdown leakage has close-to-linear I-V behavior and an equivalent resistance of ~ 103-104 Ω, while typical soft breakdown paths have high non-linear, power law I-V behavior and equivalent resistance above 105-106 Ω [82]. The complete circuit of the operational amplifier with the two-stage structure including gate-oxide breakdown model is shown in Fig.
3.35. The breakdown resistances of RBD6, RBD7 and RBD8 can be used to simulate the impact of hard and soft breakdowns on performances of the operational amplifier with the two-stage structure. The non-inverting node of the operational amplifiers with the two-stage structure is biased by the AC sinusoid signal of 500-mV (peak-to-peak amplitude) plus DC offset voltage of 1.25 V with frequency of 5 kHz. The output capacitive load is set to 10 pF, and the supply voltage VDD was set to 2.5 V. The simulated output voltage swing waveform of operational amplifier with the two-stage structure under different breakdown resistances RBD6, RBD7, and RBD8 is shown in Fig.
3.36. Comparing with Fig. 3.34, the hard breakdowns have been occurred on M6, M7, and M8 devices in two-stage operational amplifier after DC stress.
3.1.5.2. Large-Signal Transition Stress
In order to investigate and understand the impact of hard and soft breakdowns on performances of the operational amplifier with the two-stage structure under large-signal transition stress, the complete circuits including the gate-oxide breakdown model are shown in Fig. 3.37. The simulated dependence of high and low
output voltage levels of the operational amplifier with the two-stage structure under the different resistances RBD8 and RBD9 is shown in Fig. 3.38. The high output voltage level and low output voltage level of operational amplifier with the two-stage structure are degraded by oxide breakdown occurred on M8 and M9 devices, respectively. Comparing Figs. 3.32 and 3.38, the breakdown location in the operational amplifier with the two-stage structure is occurred on M8 and M9 devices after large-signal transition stress.
3.2.6. Summary
The impact of MOSFET gate-oxide reliability on CMOS operational amplifiers with the two-stage (non-stacked) and folded-cascode (stacked) structures has been investigated and analyzed. The tested structures of the operational amplifiers including both the unity-gain buffer (close-loop) and comparator (open-loop) configurations are stressed under different input frequencies and signals. Because the DC operating point of the analog circuits is changed due to the gate-oxide degradation, the small-signal performances of the operational amplifier with the two-stage structure are seriously degraded after the stress. The performances of the operational amplifier with the two-stage structure under the close-loop configuration are damaged more easily than that under the open-loop configuration after the stress. The gate-oxide reliability in the CMOS analog circuits can be improved by the stacked structure under small-signal input and output applications. But, the large-signal transition still causes some degradation on the circuit performances of the operational amplifier with the folded-cascode (stacked) structure.
3.3. Conclusion
Chapter 3 has investigated and analyzed the impact of gate-oxide breakdown on CMOS analog amplifiers. The impact of gate-oxide reliability on CMOS common-source amplifiers with the non-stacked and stacked diode-connected active load structures has been investigated and analyzed under the DC stress, AC stress with DC offset, and large-signal transition stress. The small-signal parameters of the common-source amplifier with the non-stacked diode-connected active load structure
are seriously degraded than that with non-stacked diode-connected active load structure by gate-oxide breakdown under DC, AC, and large-signal transition stresses.
The stacked structure can be used to improve the reliability of analog circuit in nanoscale CMOS process. The impact of soft breakdown, hard breakdown, and breakdown location on circuit performances of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures has been investigated and analyzed. The hard gate-oxide breakdown has more serious impact on performances of the common-source amplifier with the diode-connected active load. The impact of MOSFET gate-oxide reliability on CMOS operational amplifiers with the two-stage (non-stacked) and folded-cascode (stacked) structures has been investigated and analyzed. The tested structures of the operational amplifiers including both the unity-gain buffer (close-loop) and comparator (open-loop) configurations are stressed under different input frequencies and signals. Because the DC operating point of the analog circuits is changed due to the gate-oxide degradation, the small-signal performances of the operational amplifier with the two-stage structure are seriously degraded after the stress. The performances of the operational amplifier with the two-stage structure under the close-loop configuration are damaged more easily than that under the open-loop configuration after the stress. The gate-oxide reliability in the CMOS analog circuits can be improved by the stacked structure under small-signal input and output applications. But, the large-signal transition still causes some degradation on the circuit performances of the operational amplifier with the folded-cascode (stacked) structure. The optimized design solution to further overcome such degradation from the stress of large-signal transition on the operational amplifiers should be an important challenge to analog circuits in the nanoscale CMOS technology.
Table 3.1
Device Dimensions of Common-Source Amplifiers With the Non-Stacked and Stacked Diode-Connected Active Load Structures
Table 3.2
Comparisons of Common-Source Amplifiers With the Non-Stacked and Stacked Diode-Connected Active Load Structures among Three Overstress Conditions
Table 3.3
Device Dimensions of Operational Amplifiers With the Two-Stage or Folded-Cascode Structures
Table 3.4
Comparisons of Operational Amplifiers With the Two-Stage or Folded-Cascode Structures among Three Overstress Conditions
(a)
(b)
Fig. 3.1. Complete circuits of the common-source amplifiers with the (a) non-stacked and (b) stacked diode-connected active load structures.
Fig. 3.2. The measured setup for common-source amplifiers with the non-stacked and stacked diode-connected active load structures under DC stress to investigate the impact of gate-oxide reliability to circuit performances.
Fig. 3.3. The dependence of the small-signal gain on the stress time of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures under the DC stress.
(a)
(b)
(c)
Fig. 3.4. The input and output signal waveforms on the different stress times of the common-source amplifier with the non-stacked diode-connected active load structure under the DC stress. (a) Stress time = 0 min., (b) Stress time = 980 min., and (c) Stress time = 2000 min.
Fig. 3.5. The dependence of the unity-gain frequency on the stress time of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures under the DC stress.
Fig. 3.6. The dependence of the output DC voltage level on the stress time of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures under the DC stress.
Fig. 3.7. The measured setup for common-source amplifiers with the non-stacked and stacked diode-connected active load structures under AC stress with DC offset to investigate the impact of gate-oxide reliability to circuit performances.
Fig. 3.8. The dependence of the small-signal gain on the stress time of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures under the stress of the AC small-signal input with DC offset.
Fig. 3.9. The measured setup for common-source amplifiers with the non-stacked and stacked diode-connected active load structures under large-signal transition stress to investigate the impact of gate-oxide reliability to circuit performances.
Fig. 3.10. The dependences of the high and low output voltage levels (VH and VL) at the output nodes of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures on the stress time under stress of large-signal transition.
(a)
(b)
(c)
Fig. 3.11. The input and output signal waveforms on the different stress times of the common-source amplifier with the non-stacked and stacked diode-connected active load structures under the large-signal transition stress. (a) Stress time = 0 hour, (b) Stress time = 12 hours, and (c) Stress time = 42 hours.
Fig. 3.12. The measured dependence of power supply current IVDD of the common-source amplifiers with the non-stacked and stacked diode-connected active load structures on stress time under DC stress.
Fig. 3.13. The complete circuit of the common-source amplifier with the non-stacked diode-connected active load structure including the gate-oxide breakdown model.
Fig. 3.14. The simulated dependence of power supply current IVDD of the common-source amplifier with the non-stacked diode-connected active load structure under different resistances of RBD1 and RBD2.
Fig. 3.15. The simulated dependence of small-signal gain and output DC voltage level of the common-source amplifier with the non-stacked diode-connected active load structure under different resistances RBD2.
Fig. 3.16. The complete circuit of the common-source amplifier with the stacked diode-connected active load structure including the gate-oxide breakdown model after large-signal transition stress.
Fig. 3.17. The simulated dependence of high and low output voltage levels (VH and VL) of the common-source amplifier with the non-stacked diode-connected active load structure under different resistances of RBD1 and RBD2 after large-signal transition stress.
Fig. 3.18. The simulated dependence of high and low output voltage levels (VH and VL) of the common-source amplifier with the stacked diode-connected active load structure under different resistances of RBD3, RBD4, RBD5, and RBD6 after large-signal transition stress.
(a)
(b)
Fig. 3.19. The complete circuits of the operational amplifiers with the (a) two-stage and (b) folded-cascode circuit structures.
VDD (2.5 V)
VIN (1.25 V)
OPAMP
CL (10 pF) VOUT _
+
Fig. 3.20. The unity-gain buffer configuration for operational amplifiers under DC stress to investigate the impact of gate-oxide reliability to circuit performances.
100 101 102 103 104 105 106 107
Fig. 3.21. The fresh frequency responses of the operational amplifiers with the (a) two-stage, and (b) folded-cascode, structures operating in the unity-gain buffer.
0 1k 2k 3k 4k
Fig. 3.22. The dependence of the small-signal gain on the stress time of the operational amplifiers with the two-stage or folded-cascode structures operating in the unity-gain buffer under the DC stress.
Fig. 3.23. The dependence of the unity-gain frequency on the stress time of the operational amplifiers with the two-stage or folded-cascode structures operating in the unity-gain buffer under the DC stress.
0 1k 2k 3k 4k 156
158 160 162 164 166 168 170 172 174
Phase Margin (Degree)
Stress Time (Min.)
Two-Stage OPAmp Folded-Cascode OPAmp
Fig. 3.24. The dependence of the phase margin on the stress time of the operational amplifiers with the two-stage or folded-cascode structures operating in the unity-gain buffer under the DC stress.
Fig. 3.25. The dependence of the output-voltage swing on the stress time of the operational amplifiers with the two-stage or folded-cascode structures operating in the unity-gain buffer under the DC stress.
0 1k 2k 3k 4k 0
10 20 30 40 50 60
Offset Voltage (mV)
Stress Time (Min.)
Two-Stage OPAmp Foled-Cascode OPAmp
Fig. 3.26. The dependence of the offset voltage on the stress time of the operational amplifiers with the two-stage or folded-cascode structures operating in the unity-gain buffer under the DC stress.
0 1k 2k 3k 4k
Fig. 3.27. The dependence of the rise and fall times on the stress time of the operational amplifiers with the two-stage or folded-cascode structures operating in the unity-gain buffer under the DC stress. (a) and (b) two-stage operational amplifier. (c) folded-cascode operational amplifier.
0 1k 2k 3k 4k
Fig. 3.28. The dependence of the PSRR on the stress time of the operational amplifiers with the two-stage or folded- cascode structures operating in the unity-gain buffer under the DC stress.
Fig. 3.29. The unity-gain buffer configuration for operational amplifiers under the stress of AC small-signal input with DC offset to investigate the impact of gate-oxide reliability to circuit performances.
0 1k 2k 3k 4k 5k
Fig. 3.30. The dependence of the unity-gain frequency on the stress time of the operational amplifiers with the two-stage structure under the stress of the AC small-signal input with DC offset.
Fig. 3.31. The comparator configuration for operational amplifiers under the stress of large-signal transition to investigate the impact of gate-oxide reliability to circuit performances.
Fig. 3.32. The dependences of the high and low voltage levels at the output node on the stress time under stress of large-signal transition. The operational amplifiers with the two-stage or folded-cascode structures are stressed under the comparator configuration.
0 1 2 3 4 5 6 7
0.9 1.2 1.5 1.8 2.1 2.4 2.7
Unity -Ga in Fre que ncy (MHz)
Stress Time (Day)
Two-Stage OPAmp Folded-Cascode OPAmp
Fig. 3.33. The dependence of the unity-gain frequency on the stress time under the stress of large-signal transition. The operational amplifiers with the two-stage or folded-cascode structures are stressed under the comparator configuration.
Fig. 3.34. The measured output voltage swing waveform of operational amplifier with the two-stage structure after DC stress.
Fig. 3.35. The complete circuit of the operational amplifier with the two-stage structure including gate-oxide breakdown model under DC stress.
Fig. 3.36. The simulated output voltage swing waveform of operational amplifier with the two-stage structure under different breakdown resistances RBD6, RBD7, and RBD8.
Fig. 3.37. The complete circuit of the operational amplifier with the two-stage structure including gate-oxide breakdown model under large-signal transient stress.
Fig. 3.38. The simulated high and low output voltage levels of operational amplifier with the two-stage structure under different breakdown resistances RBD8 and RBD9.
CHAPTER 4
Circuit Performance Degradation of Switched- Capacitor Circuit With Bootstrapped Technique due to Gate-Oxide Overstress
The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on the MOS switch in switched-capacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of the SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on the switch device degrades the circuit performance of bootstrapped switch technique.
4.1. Background
The switched-capacitor circuit is an important building block in analog integrated circuits, such as analog-to-digital data converter (ADC). The high-speed and high-resolution analog-to-digital data converter needs a high performance switched-capacitor circuit. The low-supply voltage will degrade the performance of the switched-capacitor circuit due to the nonlinear effects of the MOSFET switch such as body effect, turn-on resistance variation, charge injection, and clock feedthrough [84], [85], [94]-[100].
The bootstrapped switch [84], [85], [94], [95] and switched-opamp (switched operational amplifier) techniques [96]-[100] have been widely used in low-voltage
switched-capacitor circuit. The switched-opamp technique is not suitable for high-speed switched-capacitor circuit, because it needs much more time to turn opamp on/off than to turn switch on/off [97]. The bootstrapped technique provided a constant voltage between the gate and drain nodes of the MOS switch is used to improve the performances of low-voltage and high-speed switched-capacitor circuit.
However, the bootstrapped technique causes the gate-oxide overstress on MOS switch to degrade the lifetime of switch device [84]. The gate-oxide reliability of MOS switch in the low-voltage and high-speed switched-capacitor circuit with the bootstrapped technique is a very important reliability issue. The suitable device size design for the bootstrapped switch circuit [84], the thick-oxide MOSFET device [85], and the drain extended MOSFET device [94] can be used to avoid the gate-oxide overstress on the switch devices. Some design techniques of limit gate voltage in bootstrapped switch circuit had been proposed [95]. The impact of gate-oxide reliability on circuit performance of switched-capacitor circuit with bootstrapped technique wasn’t investigated in the previous works [84], [85], [94], [95].
In this work, the impact of gate-oxide reliability on MOS switch in the switched-capacitor circuit with the bootstrapped technique is investigated with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process [101]. The time-domain and frequency-domain circuit performances of the SHA with the unity-gain buffer are measured after the gate-oxide overstress on the MOS switch.
4.2. Bootstrapped Technique with Gate-Oxide Reliability
The conceptual schematic of the bootstrapped technique for switched-capacitor circuit is shown in Fig. 4.1(a). The basic schematic includes the signal MOS switch MS, five ideal switches S1-S5, and a capacitor Cb. The CLK1 and CLK2 clock signals are the out-of-phase signals. When CLK1 is low and CLK2 is high (under sampling mode), the S3 and S4 switches charge the capacitor Cb to the supply voltage VDD,and the S5 switch is used to turn off the switch device MS. When CLK1 is high and CLK2
is low (under hold mode), the S1 and S2 switches change the capacitance Cb in series with the input signal VIN and connect to the gate of switch device MS, such that the gate-to-source voltage across the switch device MS is equal to the supply voltage VDD.
The gate voltage of switch device MS will be charged to VIN+VDD, which is larger than the supply voltage. The detailed circuit implementation is shown in Fig. 4.1(b) [102]. The M1, M2, M3, M4 and M5 correspond to the five ideal switches S1-S5 of Fig.
4.1(a). The M6 transistor is added to reduce the maximum drain-to-source voltage (VDS) of M5 transistor to avoid the gate-oxide overstress. The capacitor Cb must be large enough to supply charge to the gate of switch device in addition to all parasitic capacitors in the charge path. Moreover, charge sharing will significantly reduce the boosted voltage [84].
The sampling capacitor CS in the switched-capacitor circuit with the bootstrapped technique is usually designed with several pF to improve the circuit performance. If the rise time of the voltage at gate node of switch device is too fast, a large voltage could exist across the gate oxide of switch device to degrade the lifetime of switch device, before a channel is formed to equalize the potential between the source and drain. In order to explain the gate-oxide transient overstress event in switched-capacitor circuit with bootstrapped technique, the simulated waveforms of the bootstrapped switch circuit are shown in Fig. 4.2. The drain node of switch device is driven by an input signal VIN, and the source node of switch device is connected to a large sampling capacitor. As the switch device turns on, an approximate voltage of VIN + VDD will be generated on the gate node to keep the constant voltage VDD
between the gate and drain nodes of switch device. Before a channel is formed and before the sampling capacitor is charged to supply voltage VDD, an excessive voltage
between the gate and drain nodes of switch device. Before a channel is formed and before the sampling capacitor is charged to supply voltage VDD, an excessive voltage