Gate Tunneling Leakage Current

According to the SIA roadmap [1], CMOS with gate length below 70 nm will need an oxide thickness of less than 1.5 nm, which corresponds to two to three layers of silicon dioxide atoms.With such a thin gate oxide, direct tunneling occurs resulting in an exponential increase of gate leakage current [25]-[31]. The resulting gate leakage current will increase the power dissipation and will deteriorate the device performance and circuit stability for VLSI circuits. Control of off-state drain leakage (Ioff) and on-state gate leakage (IG) is one of the most important issues for scaling MOSFETs toward the 0.10 μm regime [25]-[31]. For deep submicron technology, as effective gate length decreases, the leakage increases because of the following scaling trends: 1) subthreshold leakage (Isub)increases exponentially due to threshold voltage reduction [29]; 2) gate edge-direct-tunneling leakage (IEDT) and gate-induced drain-leakage (IGIDL) increase exponentially due to reduced gate oxide thickness [30], [31]; 3) bulk band-to-band-tunneling leakage (IB-BTBT) increases exponentially due to increased lightly doped-drain (LDD) or pocket-doping concentrations [29]. The cross section of the NMOSFET structure and drain leakage components are schematically shown in Fig.

1.7 [28]. The off-state drain leakage (Ioff) and on-state gate leakage (IG) of MOSFET will increase the power consumption and degrade the performances of integrated circuit in advanced CMOS technology. The high-K gate dielectrics of MOSFET can be used to avoid the gate leakage effect in advanced CMOS technology [32]-[34].

1.2. Issues of Analog Circuit Design and Reliability in Low-Voltage CMOS Technology

The desire for portability of electronic equipment generated a need for low power

systems in battery-operated products, such as cell phones, PDAs and notebooks. The device dimension of transistor has been scaled toward the nanometer region and the power supply voltage of chips in the nanoscale CMOS technology has been also decreased due to the reliability and power consumption issues [1]. Voltage reductions guarantee the reliability devices to low the electrical fields inside oxide layers of MOSFET. As shown in Table. 1.1, the power supply voltage is decreased and the oxide thickness is thinner when the process is scaled down. Because of noise and offset voltage constraints, the minimum size transistors cannot be used in analog circuit. However, scaling results in better performance in digital circuit. When analog circuit operates in low voltage, the main constraints are the device noise level and the threshold voltage (VTH). The reduction of threshold voltage is dependent on the device technology. High threshold voltage gives better noise immunity and lower threshold voltage reduces the noise margin to result in poor signal-to-noise ratio (SNR) [35]. In order to get the better performance of analog circuit in low-voltage CMOS technology, a possible solution to get higher DC voltage on-chip is multiplication. However, this technique is noisy and not compatible with sensitive analog circuit. Another problem of this technique is gate-oxide reliability. Many design technique of analog circuit in low-voltage CMOS technology have been proposed, such as MOSFET operated in sub-threshold region [35]-[37], bulk driven transistors [35], [36], [38], [39], self-cascode structures [35], floating gate approach [35], [40]-[44], and level shifter techniques [35], [45]-[47].

In general, the VLSI productions have lifetime of 10 years, but the thin gate-oxide thickness of the MOS transistor has many problems, such as gate-oxide breakdown, tunneling current, and hot carrier effect that will degrade the lifetime of the MOS transistor. Another important problem in low-voltage CMOS technology is the gate-oxide reliability. In modern CMOS very large scale integrated circuits (VLSIs) including digital signal processor and embedded analog circuitry, the digital logic or digital logic circuits are generally implemented using thin-oxide devices. However, analog circuitry needs to be operated at a higher supply voltage than the nominal supply voltage of thin-oxide devices to achieve a wide dynamic range performance or meet the compatibility requirement with standardized protocols or with ICs from previous generations [48]. High-voltage tolerance of analog circuit design technique in nanoscale CMOS technology has been proposed [48]. Therefore, to improve the gate-oxide reliability of MOS transistor and to investigate the effect of gate-oxide breakdown on CMOS circuit performances will become more important in the nanometer CMOS technology. The impact of gate-oxide reliability on CMOS digital and RF

circuit has been investigated [49]-[52]. Reference [49] has reported that the oxide breakdown do not affect the digital circuit operation. Only the power consumption of digital circuit will be increased due to the gate-oxide breakdown. Reference [50] has reported the performances of dynamic digital circuit are degraded by gate-oxide breakdown. In [51], [52], the performances of RF and SRAM circuits are also degraded by gate-oxide breakdown.

However, the impact of gate-oxide breakdown on CMOS analog circuits did not have particular report.

Therefore, in this dissertation, several sub-1-V bandgap reference circuits and the impact of gate-oxide reliability on analog circuits in low-voltage CMOS technology are investigated and presented.

1.3. Organization of This Dissertation

In Chapter 2, a new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm × 106 μm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from -10 °C to 120 °C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10 kHz. The new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic NPN and PNP BJT devices in CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-μm CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/°C from 0 °C to 100 °C. With 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz.

In Chapter 3, the influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the non-stacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test conditions of this work

include the DC stress, AC stress with DC offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output DC voltage levels, are measured to verify the impact of gate-oxide reliability on circuit performances of the common-source amplifiers with diode-connected active load. The small-signal parameters of the common-source amplifier with the non-stacked diode-connected active load structure are stronger degraded than that with non-stacked diode-connected active load structure due to gate-oxide breakdown under analog and digital applications. The common-source amplifiers with diode-connected active load are not functional operation under digital application due to gate-oxide breakdown. The impact of soft and hard gate-oxide breakdowns on common-source amplifiers with non-stacked and stacked diode-connected active load structures has been analyzed and discussed. The hard breakdown has more serious impact to the common-source amplifiers with diode-connected active load. The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the DC stress, AC stress with DC offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. A simple equivalent device model of gate-oxide reliability for CMOS devices in analog circuitsis investigated and simulated.

In Chapter 4, the MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated with the sample-and-hold amplifier in a 130-nm CMOS process. After overstress on the MOS switch of SHA with open-loop configuration, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device will degrade the performance of bootstrapped switch technique.

In Chapter 5, the thin gate oxide causes the large gate tunneling leakage innanoscale CMOS technology. In this work, the influence of MOS capacitor, as loop filter, with gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated and analyzed. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter. Overview on the prior designs of gate tunneling leakage compensation technique to reduce the gate tunneling leakage on MOS capacitor as loop filter in PLL is provided in this work.

Chapter 6 presents a new proposed gate bias voltage generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon LTPS thin-film transistors (TFTs). The new proposed gate bias voltage generating circuit with threshold-voltage compensation has been successfully verified in a 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under biasing voltage of 3 V.

The new proposed gate bias voltage generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by LTPS process on glass substrate for active matrix LCD (AMLCD) panel.

Chapter 7 summarizes the main results of this dissertation. Then, some suggestions for the future works are also addressed in this chapter.

Table 1.1

Key Features of the Semiconductor Scaling Trend (High-Performance Logic Technology) [1]

Fig. 1.1. Formation of traps in the gate oxide of MOS transistor.

Fig. 1.2. Creation of conduction path through traps in the gate oxide of MOS transistor.

Fig. 1.3. Increased traps in gate oxide of MOS transistor after Conduction.

Fig. 1.4. Cross section of the gate oxide of MOS transistor after hard gate oxide breakdown.

Fig. 1.5. Hot carrier injection in CMOS technology [17].

Fig. 1.6. Schematic of the Si/oxide interface of a MOSFET. The dangling Si bonds are present due to the mismatch between the ordered channel and amorphous oxide. These act as interface traps unless they are passivated by hydrogen annealing. NBTI induces the dissociation of the Si–H bonds causing hydrogen to diffuse away from the interface [24].

Fig. 1.7. The cross section of the NMOSFET structure and drain leakage components [28].

CHAPTER 2

CMOS Bandgap Reference Circuit With Sub-1-V Operation

In this chapter,two sub-1-V CMOS bandgap voltage references without using low-threshold-voltage device are presented. First, the new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm × 106 μm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from -10 °C to 120 °C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10 kHz. Second, a new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic NPN and PNP BJT devices in CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-μm CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/°C from 0 °C to 100 °C. With 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz.

2.1. CMOS Bandgap Reference Circuit for Sub-1-V Operation Without Extra Low-Threshold-Voltage Device

2.1.1. Background

Low voltage and low power are two important design criteria in both analog and digital systems. It has been expected that the whole electronic system will be operated down to a single 1-V supply in near future. The bandgap reference (BGR) generators which can be operated under 1-V supply have been widely used in DRAM, flash memories, and analog-to-digital converter (ADC). So far, many techniques have been proposed to develop voltage or current references, which can be almost independent to temperature and power-supply voltage. The bandgap reference is the major design to provide a precision voltage reference with low sensitivity to the temperature and the supply voltage.

When CMOS technologies enter the nano-scale eras, the demand for battery-operated portable equipments will increase. The supply voltage has been scaled down from 1.8 V (in 0.18-μm technology) to 1.2 V (in 0.13-μm technology), and will drop to only 0.9 V in the next generation technology [53]. In CMOS technology, the parasitic vertical bipolar junction transistor (BJT) had been commonly used to implement P-N junction of the bandgap reference. But, the traditional CMOS bandgap reference circuits did not work in sub-1-V supply voltage. The reason, that the minimum supply voltage can not be lower than 1 V, is constrained by two factors.

One is the bandgap voltage of around 1.25 V in silicon [54]-[63], which exceeds 1 V supply. The other factor is that the low-voltage design of the proportional to absolute temperature current generation loop is limited by the input common-mode voltage of the amplifier [54], [57]. These two limitations can be solved by using the resistive subdivision methods [55], [59], low-threshold voltage (or native) device [58]-[60], BiCMOS process [57], or DTMOST device [61]. However, those approaches often require specialized processes and characterization, which increase fabrication cost and process steps.

In this work, a new bandgap reference is proposed, which can be successfully operated with sub-1-V supply in a standard 0.25-μm CMOS process without special process technology [64]. Without laser trimming, the new proposed bandgap voltage reference has been proven in the silicon chip with a stable output voltage VREF of 238.2 mV at room temperature and a temperature coefficient of 58.1 ppm/°C under VDD power supply of 0.85 V.

2.1.2. Traditional Bandgap Reference Circuit

A typical implementation of bandgap reference in CMOS technology is shown in Fig. 2.1. In this circuit, the output is the sum of a base-emitter voltage (VEB) of BJT and the voltage drop across the upper resistor. The BJTs (Q1 and Q2) are typically implemented by the diode-connected vertical PNP bipolar junction transistors. The output voltage of the traditional bandgap reference circuit can be written as

2 1 second item in (2.1) is proportional to the absolute temperature (PTAT), which is used to compensate the negative temperature coefficient of VEB. Usually, the VPTAT voltage comes from the thermal voltage VT with a temperature coefficient about + 0.085 mV/°C, which is quite smaller than that of VEB. After multiplying VPTAT with an appropriate factor and summing with VEB, the bandgap reference will have a very low sensitivity to temperature. Hence, if a proper ratio of resistors is kept, an output voltage with very low sensitivity to temperature can be obtained. In general, the VREF

is about 1.25 V in CMOS process, so that the traditional bandgap reference circuit can not be operated in low voltage application, such as 1 V or below.

2.1.3. New Proposed Bandgap Reference Circuit

The design concept of the new proposed bandgap reference is that the two voltages (which are proportional to VEB and VT, respectively) are generated from the same feedback loop. The two-stage operational amplifier with p-channel input is used in this new proposed bandgap reference. The p-channel input has a lower input common-mode voltage than that of the n-channel input to keep the transistors working in the saturation region.

The new proposed bandgap reference is shown in Fig. 2.2, which uses the resistive subdivision R1a, R1b,R2a, and R2b to reduce the input common-mode voltage of the amplifier. The voltages V1 and V2 in Fig. 2.2 have a negative temperature

coefficient as that of VEB. In the traditional bandgap reference, the negative input of the operational amplifier is connected to VEB2, whose value is varying from 0.65 V to 0.45 V when the temperature is changed from 0 °C to 100 °C. The minimum supply voltage (VDD) of the traditional bandgap reference circuit needs VEB2+2|VDSsat|+|VTHp|.

The VTHp is the threshold voltage of PMOS. The supply voltage of the traditional bandgap reference is more than 1 V. In Fig. 2.2, the dimensions of PMOS devices M1

and M2 are kept the same. The resistance of R1a and R2a is the same, and the resistance of R1b and R2b is also the same. Following the KCL at the nodes of V1 and V2 in Fig.

2.2, the node equation can be written as

2 reference voltage VREF can be expressed as

1 1

The item of VREF-TRAD in (2.4) is identical to the traditional reference voltage in (2.1).

In order to achieve sub-1-V operation, the ratio of R1b / (R1a+R1b) is used to scale down the reference voltage level. Therefore, the minimum supply voltage of the new proposed bandgap reference can be effectively reduced to only

( ) 2 2

DD Min THp DSsat

V =V +V + V . (2.5) The new proposed bandgap reference can be operated under sub-1-V supply voltage.

The whole complete circuit to realize the proposed sub-1-V bandgap reference is shown in Fig. 2.3. The circuit is composed of a bias circuit, a bandgap core, two

startup circuits, and a two-stage operational amplifier. The bandgap reference circuit has two stable points. To ensure that it ends up to the correct state, a startup circuit must be added. The startup circuit for the bias circuit is used to avoid the bias circuit working in the zero-current state, which is realized by MS1a∼MS3a in Fig. 2.3 [55].

Similarly, another startup circuit is used to ensure that the input voltage of the amplifier is not kept at zero in the initial state. The MS1a and MS2a form a function of inverter in the startup circuit. The device dimensions (W/L) of MS2a and MS2b are chosen to be much less than one. When the circuit operates in zero-current state, the gate voltages of MS1a and MS1b are pulled high and close to VDD. The drain voltages of MS2a and MS2b are pulled low to turn on the MS3a and MS3b, which inject current to the bandgap core circuitry (by MS3b) and the bias circuit (by MS3a). The drain voltages of MB3 and M4 are decreased, therefore the bandgap core circuitry and bias circuit start to operate. Once the drain voltage of MB4 and the gate voltages of M1, M2, MA1, and MA6 are decreased, the drain voltages of MS1a and MS1b are pulled high to cut off MS3a

and MS3b. The device dimensions (W/L) of MS2a and MS2b are critical since the loop of the bandgap reference could be destroyed, if MS3a or MS3b were not completely cut off after startup. To ensure a complete cutoff operation of MS3a and MS3b, the device dimensions (W/L) of MS3a and MS3b should be designed with the considerations of both maximum supply voltage and operating temperature [55]. The capacitors C1 and C2 are used to stabilize the circuit. The bulk and the source of the input pair transistors MA2 and MA3 in the amplifier should be connected together to avoid the body effect.

In real-world applications, the power supply voltage is never perfect. It consists

In real-world applications, the power supply voltage is never perfect. It consists